diff --git a/src/VGATimingGenerator_test.vhd b/src/VGATimingGenerator_test.vhd
index c961859..e80ceda 100644
--- a/src/VGATimingGenerator_test.vhd
+++ b/src/VGATimingGenerator_test.vhd
@@ -27,11 +27,11 @@ end entity VGATimingGenerator_test;
 architecture RTL of VGATimingGenerator_test is
     signal R_PixelReady : std_logic_vector(1 downto 0);
 
-    signal R_LineCounter : unsigned(19 downto 0) := (others => '0');
+    signal R_LineCounter   : unsigned(19 downto 0) := (others => '0');
 
     signal R_VSync : std_logic;
 
-    signal CLK_FB   : std_logic;
+    signal CLK_FB : std_logic;
     signal PixelCLK : std_logic;
 begin
 
@@ -54,13 +54,13 @@ begin
     port map
     (
         CLK0  => CLK_FB,
-        CLKFX => PixelCLK,
+        CLKDV => PixelCLK,
         CLKFB => CLK_FB,
         CLKIN => I_CLK
     );
 
     VGAColorGenerator : process (PixelCLK)
-        variable R_SignalCounter : unsigned(3 downto 0) := (others => '0');
+        variable R_SignalCounter : unsigned(3 downto 0)  := (others => '0');
     begin
         if rising_edge(PixelCLK) then
             if R_VSync = '0' then
@@ -110,17 +110,6 @@ begin
     end process;
 
     VGATimingGenerator : entity work.VGATimingGenerator
-        generic map(
-            G_HFront => 88,
-            G_HSync  => 44,
-            G_HBack  => 148,
-            G_HTotal => 2200,
-            G_VFront => 4,
-            G_VSync  => 5,
-            G_VBack  => 36,
-            G_VTotal => 1125
-        )
-
         port map
         (
             I_CLK        => PixelCLK,