HDL/AXI-HS-Scheduler
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0xMax42
2025-04-21 17:29:28 +02:00
commit f98e7d56f4
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_Handshaking_Scheduler_16 is
generic (
G_DataWidth : integer := 8;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus P0 @dir in P0 interface
I_P0_Valid : in std_logic := '0';
O_P0_Ready : out std_logic := '0';
I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P1 @dir in P1 interface
I_P1_Valid : in std_logic := '0';
O_P1_Ready : out std_logic := '0';
I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P2 @dir in P2 interface
I_P2_Valid : in std_logic := '0';
O_P2_Ready : out std_logic := '0';
I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P3 @dir in P3 interface
I_P3_Valid : in std_logic := '0';
O_P3_Ready : out std_logic := '0';
I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P4 @dir in P4 interface
I_P4_Valid : in std_logic := '0';
O_P4_Ready : out std_logic := '0';
I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P5 @dir in P5 interface
I_P5_Valid : in std_logic := '0';
O_P5_Ready : out std_logic := '0';
I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P6 @dir in P6 interface
I_P6_Valid : in std_logic := '0';
O_P6_Ready : out std_logic := '0';
I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P7 @dir in P7 interface
I_P7_Valid : in std_logic := '0';
O_P7_Ready : out std_logic := '0';
I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P8 @dir in P8 interface
I_P8_Valid : in std_logic := '0';
O_P8_Ready : out std_logic := '0';
I_P8_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P9 @dir in P9 interface
I_P9_Valid : in std_logic := '0';
O_P9_Ready : out std_logic := '0';
I_P9_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P10 @dir in P10 interface
I_P10_Valid : in std_logic := '0';
O_P10_Ready : out std_logic := '0';
I_P10_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P11 @dir in P11 interface
I_P11_Valid : in std_logic := '0';
O_P11_Ready : out std_logic := '0';
I_P11_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P12 @dir in P12 interface
I_P12_Valid : in std_logic := '0';
O_P12_Ready : out std_logic := '0';
I_P12_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P13 @dir in P13 interface
I_P13_Valid : in std_logic := '0';
O_P13_Ready : out std_logic := '0';
I_P13_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P14 @dir in P14 interface
I_P14_Valid : in std_logic := '0';
O_P14_Ready : out std_logic := '0';
I_P14_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P15 @dir in P15 interface
I_P15_Valid : in std_logic := '0';
O_P15_Ready : out std_logic := '0';
I_P15_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus Out @dir out Output interface
O_Out_Valid : out std_logic := '0';
I_Out_Ready : in std_logic := '0';
O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
O_Out_Address : out std_logic_vector(3 downto 0) := (others => '0')
--@ @end
);
end entity AXI_Handshaking_Scheduler_16;
architecture Rtl of AXI_Handshaking_Scheduler_16 is
signal R_SelectRotator : unsigned(3 downto 0) := (others => '0');
signal R1_SelectRotator : unsigned(3 downto 0) := (others => '0');
signal C_Select : std_logic_vector(15 downto 0) := (others => '0');
signal C_Code : std_logic_vector(3 downto 0) := (others => '0');
signal R_Code : std_logic_vector(3 downto 0) := (others => '0');
signal C_CodeUnrotated : std_logic_vector(3 downto 0) := (others => '0');
signal S_P0_InBufferEnable : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_InBufferEnable : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_InBufferEnable : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_InBufferEnable : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P4_InBufferEnable : std_logic := '0';
signal S_P4_Ready : std_logic := '0';
signal S_P4_Valid : std_logic := '0';
signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P5_InBufferEnable : std_logic := '0';
signal S_P5_Ready : std_logic := '0';
signal S_P5_Valid : std_logic := '0';
signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P6_InBufferEnable : std_logic := '0';
signal S_P6_Ready : std_logic := '0';
signal S_P6_Valid : std_logic := '0';
signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P7_InBufferEnable : std_logic := '0';
signal S_P7_Ready : std_logic := '0';
signal S_P7_Valid : std_logic := '0';
signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P8_InBufferEnable : std_logic := '0';
signal S_P8_Ready : std_logic := '0';
signal S_P8_Valid : std_logic := '0';
signal S_P8_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P9_InBufferEnable : std_logic := '0';
signal S_P9_Ready : std_logic := '0';
signal S_P9_Valid : std_logic := '0';
signal S_P9_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P10_InBufferEnable : std_logic := '0';
signal S_P10_Ready : std_logic := '0';
signal S_P10_Valid : std_logic := '0';
signal S_P10_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P11_InBufferEnable : std_logic := '0';
signal S_P11_Ready : std_logic := '0';
signal S_P11_Valid : std_logic := '0';
signal S_P11_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P12_InBufferEnable : std_logic := '0';
signal S_P12_Ready : std_logic := '0';
signal S_P12_Valid : std_logic := '0';
signal S_P12_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P13_InBufferEnable : std_logic := '0';
signal S_P13_Ready : std_logic := '0';
signal S_P13_Valid : std_logic := '0';
signal S_P13_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P14_InBufferEnable : std_logic := '0';
signal S_P14_Ready : std_logic := '0';
signal S_P14_Valid : std_logic := '0';
signal S_P14_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P15_InBufferEnable : std_logic := '0';
signal S_P15_Ready : std_logic := '0';
signal S_P15_Valid : std_logic := '0';
signal S_P15_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_OutBufferEnable : std_logic := '0';
signal S_Out_Ready : std_logic := '0';
signal S_Out_Valid : std_logic := '0';
signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_Out_Address : std_logic_vector(3 downto 0) := (others => '0');
begin
I_P0_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_InBufferEnable,
I_Valid => I_P0_Valid,
O_Ready => O_P0_Ready,
O_Valid => S_P0_Valid,
I_Ready => S_P0_Ready
);
I_P0_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_InBufferEnable,
I_Data => I_P0_Data,
O_Data => S_P0_Data
);
I_P1_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_InBufferEnable,
I_Valid => I_P1_Valid,
O_Ready => O_P1_Ready,
O_Valid => S_P1_Valid,
I_Ready => S_P1_Ready
);
I_P1_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_InBufferEnable,
I_Data => I_P1_Data,
O_Data => S_P1_Data
);
I_P2_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_InBufferEnable,
I_Valid => I_P2_Valid,
O_Ready => O_P2_Ready,
O_Valid => S_P2_Valid,
I_Ready => S_P2_Ready
);
I_P2_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_InBufferEnable,
I_Data => I_P2_Data,
O_Data => S_P2_Data
);
I_P3_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_InBufferEnable,
I_Valid => I_P3_Valid,
O_Ready => O_P3_Ready,
O_Valid => S_P3_Valid,
I_Ready => S_P3_Ready
);
I_P3_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_InBufferEnable,
I_Data => I_P3_Data,
O_Data => S_P3_Data
);
I_P4_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P4_InBufferEnable,
I_Valid => I_P4_Valid,
O_Ready => O_P4_Ready,
O_Valid => S_P4_Valid,
I_Ready => S_P4_Ready
);
I_P4_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P4_InBufferEnable,
I_Data => I_P4_Data,
O_Data => S_P4_Data
);
I_P5_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P5_InBufferEnable,
I_Valid => I_P5_Valid,
O_Ready => O_P5_Ready,
O_Valid => S_P5_Valid,
I_Ready => S_P5_Ready
);
I_P5_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P5_InBufferEnable,
I_Data => I_P5_Data,
O_Data => S_P5_Data
);
I_P6_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P6_InBufferEnable,
I_Valid => I_P6_Valid,
O_Ready => O_P6_Ready,
O_Valid => S_P6_Valid,
I_Ready => S_P6_Ready
);
I_P6_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P6_InBufferEnable,
I_Data => I_P6_Data,
O_Data => S_P6_Data
);
I_P7_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P7_InBufferEnable,
I_Valid => I_P7_Valid,
O_Ready => O_P7_Ready,
O_Valid => S_P7_Valid,
I_Ready => S_P7_Ready
);
I_P7_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P7_InBufferEnable,
I_Data => I_P7_Data,
O_Data => S_P7_Data
);
I_P8_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P8_InBufferEnable,
I_Valid => I_P8_Valid,
O_Ready => O_P8_Ready,
O_Valid => S_P8_Valid,
I_Ready => S_P8_Ready
);
I_P8_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P8_InBufferEnable,
I_Data => I_P8_Data,
O_Data => S_P8_Data
);
I_P9_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P9_InBufferEnable,
I_Valid => I_P9_Valid,
O_Ready => O_P9_Ready,
O_Valid => S_P9_Valid,
I_Ready => S_P9_Ready
);
I_P9_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P9_InBufferEnable,
I_Data => I_P9_Data,
O_Data => S_P9_Data
);
I_P10_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P10_InBufferEnable,
I_Valid => I_P10_Valid,
O_Ready => O_P10_Ready,
O_Valid => S_P10_Valid,
I_Ready => S_P10_Ready
);
I_P10_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P10_InBufferEnable,
I_Data => I_P10_Data,
O_Data => S_P10_Data
);
I_P11_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P11_InBufferEnable,
I_Valid => I_P11_Valid,
O_Ready => O_P11_Ready,
O_Valid => S_P11_Valid,
I_Ready => S_P11_Ready
);
I_P11_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P11_InBufferEnable,
I_Data => I_P11_Data,
O_Data => S_P11_Data
);
I_P12_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P12_InBufferEnable,
I_Valid => I_P12_Valid,
O_Ready => O_P12_Ready,
O_Valid => S_P12_Valid,
I_Ready => S_P12_Ready
);
I_P12_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P12_InBufferEnable,
I_Data => I_P12_Data,
O_Data => S_P12_Data
);
I_P13_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P13_InBufferEnable,
I_Valid => I_P13_Valid,
O_Ready => O_P13_Ready,
O_Valid => S_P13_Valid,
I_Ready => S_P13_Ready
);
I_P13_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P13_InBufferEnable,
I_Data => I_P13_Data,
O_Data => S_P13_Data
);
I_P14_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P14_InBufferEnable,
I_Valid => I_P14_Valid,
O_Ready => O_P14_Ready,
O_Valid => S_P14_Valid,
I_Ready => S_P14_Ready
);
I_P14_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P14_InBufferEnable,
I_Data => I_P14_Data,
O_Data => S_P14_Data
);
I_P15_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P15_InBufferEnable,
I_Valid => I_P15_Valid,
O_Ready => O_P15_Ready,
O_Valid => S_P15_Valid,
I_Ready => S_P15_Ready
);
I_P15_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P15_InBufferEnable,
I_Data => I_P15_Data,
O_Data => S_P15_Data
);
I_PriorityEncoder_16 : entity work.PriorityEncoder_16
port map(
I_Select => C_Select,
O_Code => C_Code
);
P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid)
begin
case R_SelectRotator is when "0000" =>
C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid;
when "0001" =>
C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid;
when "0010" =>
C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid;
when "0011" =>
C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
when "0100" =>
C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
when "0101" =>
C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid;
when "0110" =>
C_Select <= S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid;
when "0111" =>
C_Select <= S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid;
when "1000" =>
C_Select <= S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid;
when "1001" =>
C_Select <= S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid;
when "1010" =>
C_Select <= S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid;
when "1011" =>
C_Select <= S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid;
when "1100" =>
C_Select <= S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid;
when "1101" =>
C_Select <= S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid;
when "1110" =>
C_Select <= S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid;
when "1111" =>
C_Select <= S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid;
when others =>
C_Select <= (others => '-');
end case;
end process;
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
begin
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
end process;
P_OutMux : process (
C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P8_Data, S_P9_Data, S_P10_Data, S_P11_Data, S_P12_Data, S_P13_Data, S_P14_Data, S_P15_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_Out_Ready)
begin
S_Out_Valid <= '0';
S_P0_Ready <= '0';
S_P1_Ready <= '0';
S_P2_Ready <= '0';
S_P3_Ready <= '0';
S_P4_Ready <= '0';
S_P5_Ready <= '0';
S_P6_Ready <= '0';
S_P7_Ready <= '0';
S_P8_Ready <= '0';
S_P9_Ready <= '0';
S_P10_Ready <= '0';
S_P11_Ready <= '0';
S_P12_Ready <= '0';
S_P13_Ready <= '0';
S_P14_Ready <= '0';
S_P15_Ready <= '0';
S_Out_Data <= (others => '-');
S_Out_Address <= C_CodeUnrotated;
case C_CodeUnrotated is when "0000" =>
S_Out_Valid <= S_P0_Valid;
S_P0_Ready <= S_Out_Ready;
S_Out_Data <= S_P0_Data;
when "0001" =>
S_Out_Valid <= S_P1_Valid;
S_P1_Ready <= S_Out_Ready;
S_Out_Data <= S_P1_Data;
when "0010" =>
S_Out_Valid <= S_P2_Valid;
S_P2_Ready <= S_Out_Ready;
S_Out_Data <= S_P2_Data;
when "0011" =>
S_Out_Valid <= S_P3_Valid;
S_P3_Ready <= S_Out_Ready;
S_Out_Data <= S_P3_Data;
when "0100" =>
S_Out_Valid <= S_P4_Valid;
S_P4_Ready <= S_Out_Ready;
S_Out_Data <= S_P4_Data;
when "0101" =>
S_Out_Valid <= S_P5_Valid;
S_P5_Ready <= S_Out_Ready;
S_Out_Data <= S_P5_Data;
when "0110" =>
S_Out_Valid <= S_P6_Valid;
S_P6_Ready <= S_Out_Ready;
S_Out_Data <= S_P6_Data;
when "0111" =>
S_Out_Valid <= S_P7_Valid;
S_P7_Ready <= S_Out_Ready;
S_Out_Data <= S_P7_Data;
when "1000" =>
S_Out_Valid <= S_P8_Valid;
S_P8_Ready <= S_Out_Ready;
S_Out_Data <= S_P8_Data;
when "1001" =>
S_Out_Valid <= S_P9_Valid;
S_P9_Ready <= S_Out_Ready;
S_Out_Data <= S_P9_Data;
when "1010" =>
S_Out_Valid <= S_P10_Valid;
S_P10_Ready <= S_Out_Ready;
S_Out_Data <= S_P10_Data;
when "1011" =>
S_Out_Valid <= S_P11_Valid;
S_P11_Ready <= S_Out_Ready;
S_Out_Data <= S_P11_Data;
when "1100" =>
S_Out_Valid <= S_P12_Valid;
S_P12_Ready <= S_Out_Ready;
S_Out_Data <= S_P12_Data;
when "1101" =>
S_Out_Valid <= S_P13_Valid;
S_P13_Ready <= S_Out_Ready;
S_Out_Data <= S_P13_Data;
when "1110" =>
S_Out_Valid <= S_P14_Valid;
S_P14_Ready <= S_Out_Ready;
S_Out_Data <= S_P14_Data;
when "1111" =>
S_Out_Valid <= S_P15_Valid;
S_P15_Ready <= S_Out_Ready;
S_Out_Data <= S_P15_Data;
when others =>
S_Out_Address <= (others => '-');
end case;
end process;
P_SelectRotator : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_CE = '1' then
if I_RST = '1' then
R_SelectRotator <= (others => '0');
R1_SelectRotator <= (others => '0');
R_Code <= (others => '0');
else
R1_SelectRotator <= R_SelectRotator;
R_Code <= C_Code;
if I_Out_Ready = '1' then
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
end if;
end if;
end if;
end if;
end process P_SelectRotator;
I_OutBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_OutBufferEnable,
I_Valid => S_Out_Valid,
O_Ready => S_Out_Ready,
O_Valid => O_Out_Valid,
I_Ready => I_Out_Ready
);
I_OutDataBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Data,
O_Data => O_Out_Data
);
I_OutAddressBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => 4,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Address,
O_Data => O_Out_Address
);
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_Handshaking_Scheduler_2 is
generic (
G_DataWidth : integer := 8;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus P0 @dir in P0 interface
I_P0_Valid : in std_logic := '0';
O_P0_Ready : out std_logic := '0';
I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P1 @dir in P1 interface
I_P1_Valid : in std_logic := '0';
O_P1_Ready : out std_logic := '0';
I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus Out @dir out Output interface
O_Out_Valid : out std_logic := '0';
I_Out_Ready : in std_logic := '0';
O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
O_Out_Address : out std_logic_vector(0 downto 0) := (others => '0')
--@ @end
);
end entity AXI_Handshaking_Scheduler_2;
architecture Rtl of AXI_Handshaking_Scheduler_2 is
signal R_SelectRotator : unsigned(0 downto 0) := (others => '0');
signal R1_SelectRotator : unsigned(0 downto 0) := (others => '0');
signal C_Select : std_logic_vector(1 downto 0) := (others => '0');
signal C_Code : std_logic_vector(0 downto 0) := (others => '0');
signal R_Code : std_logic_vector(0 downto 0) := (others => '0');
signal C_CodeUnrotated : std_logic_vector(0 downto 0) := (others => '0');
signal S_P0_InBufferEnable : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_InBufferEnable : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_OutBufferEnable : std_logic := '0';
signal S_Out_Ready : std_logic := '0';
signal S_Out_Valid : std_logic := '0';
signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_Out_Address : std_logic_vector(0 downto 0) := (others => '0');
begin
I_P0_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_InBufferEnable,
I_Valid => I_P0_Valid,
O_Ready => O_P0_Ready,
O_Valid => S_P0_Valid,
I_Ready => S_P0_Ready
);
I_P0_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_InBufferEnable,
I_Data => I_P0_Data,
O_Data => S_P0_Data
);
I_P1_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_InBufferEnable,
I_Valid => I_P1_Valid,
O_Ready => O_P1_Ready,
O_Valid => S_P1_Valid,
I_Ready => S_P1_Ready
);
I_P1_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_InBufferEnable,
I_Data => I_P1_Data,
O_Data => S_P1_Data
);
I_PriorityEncoder_2 : entity work.PriorityEncoder_2
port map(
I_Select => C_Select,
O_Code => C_Code
);
P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid)
begin
case R_SelectRotator is when "0" =>
C_Select <= S_P0_Valid & S_P1_Valid;
when "1" =>
C_Select <= S_P1_Valid & S_P0_Valid;
when others =>
C_Select <= (others => '-');
end case;
end process;
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
begin
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
end process;
P_OutMux : process (
C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P0_Valid, S_P1_Valid, S_Out_Ready)
begin
S_Out_Valid <= '0';
S_P0_Ready <= '0';
S_P1_Ready <= '0';
S_Out_Data <= (others => '-');
S_Out_Address <= C_CodeUnrotated;
case C_CodeUnrotated is when "0" =>
S_Out_Valid <= S_P0_Valid;
S_P0_Ready <= S_Out_Ready;
S_Out_Data <= S_P0_Data;
when "1" =>
S_Out_Valid <= S_P1_Valid;
S_P1_Ready <= S_Out_Ready;
S_Out_Data <= S_P1_Data;
when others =>
S_Out_Address <= (others => '-');
end case;
end process;
P_SelectRotator : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_CE = '1' then
if I_RST = '1' then
R_SelectRotator <= (others => '0');
R1_SelectRotator <= (others => '0');
R_Code <= (others => '0');
else
R1_SelectRotator <= R_SelectRotator;
R_Code <= C_Code;
if I_Out_Ready = '1' then
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
end if;
end if;
end if;
end if;
end process P_SelectRotator;
I_OutBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_OutBufferEnable,
I_Valid => S_Out_Valid,
O_Ready => S_Out_Ready,
O_Valid => O_Out_Valid,
I_Ready => I_Out_Ready
);
I_OutDataBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Data,
O_Data => O_Out_Data
);
I_OutAddressBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => 1,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Address,
O_Data => O_Out_Address
);
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_Handshaking_Scheduler_4 is
generic (
G_DataWidth : integer := 8;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus P0 @dir in P0 interface
I_P0_Valid : in std_logic := '0';
O_P0_Ready : out std_logic := '0';
I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P1 @dir in P1 interface
I_P1_Valid : in std_logic := '0';
O_P1_Ready : out std_logic := '0';
I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P2 @dir in P2 interface
I_P2_Valid : in std_logic := '0';
O_P2_Ready : out std_logic := '0';
I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P3 @dir in P3 interface
I_P3_Valid : in std_logic := '0';
O_P3_Ready : out std_logic := '0';
I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus Out @dir out Output interface
O_Out_Valid : out std_logic := '0';
I_Out_Ready : in std_logic := '0';
O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
O_Out_Address : out std_logic_vector(1 downto 0) := (others => '0')
--@ @end
);
end entity AXI_Handshaking_Scheduler_4;
architecture Rtl of AXI_Handshaking_Scheduler_4 is
signal R_SelectRotator : unsigned(1 downto 0) := (others => '0');
signal R1_SelectRotator : unsigned(1 downto 0) := (others => '0');
signal C_Select : std_logic_vector(3 downto 0) := (others => '0');
signal C_Code : std_logic_vector(1 downto 0) := (others => '0');
signal R_Code : std_logic_vector(1 downto 0) := (others => '0');
signal C_CodeUnrotated : std_logic_vector(1 downto 0) := (others => '0');
signal S_P0_InBufferEnable : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_InBufferEnable : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_InBufferEnable : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_InBufferEnable : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_OutBufferEnable : std_logic := '0';
signal S_Out_Ready : std_logic := '0';
signal S_Out_Valid : std_logic := '0';
signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_Out_Address : std_logic_vector(1 downto 0) := (others => '0');
begin
I_P0_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_InBufferEnable,
I_Valid => I_P0_Valid,
O_Ready => O_P0_Ready,
O_Valid => S_P0_Valid,
I_Ready => S_P0_Ready
);
I_P0_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_InBufferEnable,
I_Data => I_P0_Data,
O_Data => S_P0_Data
);
I_P1_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_InBufferEnable,
I_Valid => I_P1_Valid,
O_Ready => O_P1_Ready,
O_Valid => S_P1_Valid,
I_Ready => S_P1_Ready
);
I_P1_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_InBufferEnable,
I_Data => I_P1_Data,
O_Data => S_P1_Data
);
I_P2_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_InBufferEnable,
I_Valid => I_P2_Valid,
O_Ready => O_P2_Ready,
O_Valid => S_P2_Valid,
I_Ready => S_P2_Ready
);
I_P2_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_InBufferEnable,
I_Data => I_P2_Data,
O_Data => S_P2_Data
);
I_P3_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_InBufferEnable,
I_Valid => I_P3_Valid,
O_Ready => O_P3_Ready,
O_Valid => S_P3_Valid,
I_Ready => S_P3_Ready
);
I_P3_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_InBufferEnable,
I_Data => I_P3_Data,
O_Data => S_P3_Data
);
I_PriorityEncoder_4 : entity work.PriorityEncoder_4
port map(
I_Select => C_Select,
O_Code => C_Code
);
P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid)
begin
case R_SelectRotator is when "00" =>
C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
when "01" =>
C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P0_Valid;
when "10" =>
C_Select <= S_P2_Valid & S_P3_Valid & S_P0_Valid & S_P1_Valid;
when "11" =>
C_Select <= S_P3_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
when others =>
C_Select <= (others => '-');
end case;
end process;
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
begin
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
end process;
P_OutMux : process (
C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_Out_Ready)
begin
S_Out_Valid <= '0';
S_P0_Ready <= '0';
S_P1_Ready <= '0';
S_P2_Ready <= '0';
S_P3_Ready <= '0';
S_Out_Data <= (others => '-');
S_Out_Address <= C_CodeUnrotated;
case C_CodeUnrotated is when "00" =>
S_Out_Valid <= S_P0_Valid;
S_P0_Ready <= S_Out_Ready;
S_Out_Data <= S_P0_Data;
when "01" =>
S_Out_Valid <= S_P1_Valid;
S_P1_Ready <= S_Out_Ready;
S_Out_Data <= S_P1_Data;
when "10" =>
S_Out_Valid <= S_P2_Valid;
S_P2_Ready <= S_Out_Ready;
S_Out_Data <= S_P2_Data;
when "11" =>
S_Out_Valid <= S_P3_Valid;
S_P3_Ready <= S_Out_Ready;
S_Out_Data <= S_P3_Data;
when others =>
S_Out_Address <= (others => '-');
end case;
end process;
P_SelectRotator : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_CE = '1' then
if I_RST = '1' then
R_SelectRotator <= (others => '0');
R1_SelectRotator <= (others => '0');
R_Code <= (others => '0');
else
R1_SelectRotator <= R_SelectRotator;
R_Code <= C_Code;
if I_Out_Ready = '1' then
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
end if;
end if;
end if;
end if;
end process P_SelectRotator;
I_OutBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_OutBufferEnable,
I_Valid => S_Out_Valid,
O_Ready => S_Out_Ready,
O_Valid => O_Out_Valid,
I_Ready => I_Out_Ready
);
I_OutDataBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Data,
O_Data => O_Out_Data
);
I_OutAddressBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => 2,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Address,
O_Data => O_Out_Address
);
end architecture;

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build/AXI_Handshaking_Scheduler_64.vhdl Normal file
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build/AXI_Handshaking_Scheduler_8.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_Handshaking_Scheduler_8 is
generic (
G_DataWidth : integer := 8;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus P0 @dir in P0 interface
I_P0_Valid : in std_logic := '0';
O_P0_Ready : out std_logic := '0';
I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P1 @dir in P1 interface
I_P1_Valid : in std_logic := '0';
O_P1_Ready : out std_logic := '0';
I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P2 @dir in P2 interface
I_P2_Valid : in std_logic := '0';
O_P2_Ready : out std_logic := '0';
I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P3 @dir in P3 interface
I_P3_Valid : in std_logic := '0';
O_P3_Ready : out std_logic := '0';
I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P4 @dir in P4 interface
I_P4_Valid : in std_logic := '0';
O_P4_Ready : out std_logic := '0';
I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P5 @dir in P5 interface
I_P5_Valid : in std_logic := '0';
O_P5_Ready : out std_logic := '0';
I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P6 @dir in P6 interface
I_P6_Valid : in std_logic := '0';
O_P6_Ready : out std_logic := '0';
I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P7 @dir in P7 interface
I_P7_Valid : in std_logic := '0';
O_P7_Ready : out std_logic := '0';
I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus Out @dir out Output interface
O_Out_Valid : out std_logic := '0';
I_Out_Ready : in std_logic := '0';
O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
O_Out_Address : out std_logic_vector(2 downto 0) := (others => '0')
--@ @end
);
end entity AXI_Handshaking_Scheduler_8;
architecture Rtl of AXI_Handshaking_Scheduler_8 is
signal R_SelectRotator : unsigned(2 downto 0) := (others => '0');
signal R1_SelectRotator : unsigned(2 downto 0) := (others => '0');
signal C_Select : std_logic_vector(7 downto 0) := (others => '0');
signal C_Code : std_logic_vector(2 downto 0) := (others => '0');
signal R_Code : std_logic_vector(2 downto 0) := (others => '0');
signal C_CodeUnrotated : std_logic_vector(2 downto 0) := (others => '0');
signal S_P0_InBufferEnable : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_InBufferEnable : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_InBufferEnable : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_InBufferEnable : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P4_InBufferEnable : std_logic := '0';
signal S_P4_Ready : std_logic := '0';
signal S_P4_Valid : std_logic := '0';
signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P5_InBufferEnable : std_logic := '0';
signal S_P5_Ready : std_logic := '0';
signal S_P5_Valid : std_logic := '0';
signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P6_InBufferEnable : std_logic := '0';
signal S_P6_Ready : std_logic := '0';
signal S_P6_Valid : std_logic := '0';
signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P7_InBufferEnable : std_logic := '0';
signal S_P7_Ready : std_logic := '0';
signal S_P7_Valid : std_logic := '0';
signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_OutBufferEnable : std_logic := '0';
signal S_Out_Ready : std_logic := '0';
signal S_Out_Valid : std_logic := '0';
signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_Out_Address : std_logic_vector(2 downto 0) := (others => '0');
begin
I_P0_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_InBufferEnable,
I_Valid => I_P0_Valid,
O_Ready => O_P0_Ready,
O_Valid => S_P0_Valid,
I_Ready => S_P0_Ready
);
I_P0_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_InBufferEnable,
I_Data => I_P0_Data,
O_Data => S_P0_Data
);
I_P1_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_InBufferEnable,
I_Valid => I_P1_Valid,
O_Ready => O_P1_Ready,
O_Valid => S_P1_Valid,
I_Ready => S_P1_Ready
);
I_P1_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_InBufferEnable,
I_Data => I_P1_Data,
O_Data => S_P1_Data
);
I_P2_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_InBufferEnable,
I_Valid => I_P2_Valid,
O_Ready => O_P2_Ready,
O_Valid => S_P2_Valid,
I_Ready => S_P2_Ready
);
I_P2_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_InBufferEnable,
I_Data => I_P2_Data,
O_Data => S_P2_Data
);
I_P3_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_InBufferEnable,
I_Valid => I_P3_Valid,
O_Ready => O_P3_Ready,
O_Valid => S_P3_Valid,
I_Ready => S_P3_Ready
);
I_P3_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_InBufferEnable,
I_Data => I_P3_Data,
O_Data => S_P3_Data
);
I_P4_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P4_InBufferEnable,
I_Valid => I_P4_Valid,
O_Ready => O_P4_Ready,
O_Valid => S_P4_Valid,
I_Ready => S_P4_Ready
);
I_P4_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P4_InBufferEnable,
I_Data => I_P4_Data,
O_Data => S_P4_Data
);
I_P5_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P5_InBufferEnable,
I_Valid => I_P5_Valid,
O_Ready => O_P5_Ready,
O_Valid => S_P5_Valid,
I_Ready => S_P5_Ready
);
I_P5_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P5_InBufferEnable,
I_Data => I_P5_Data,
O_Data => S_P5_Data
);
I_P6_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P6_InBufferEnable,
I_Valid => I_P6_Valid,
O_Ready => O_P6_Ready,
O_Valid => S_P6_Valid,
I_Ready => S_P6_Ready
);
I_P6_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P6_InBufferEnable,
I_Data => I_P6_Data,
O_Data => S_P6_Data
);
I_P7_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P7_InBufferEnable,
I_Valid => I_P7_Valid,
O_Ready => O_P7_Ready,
O_Valid => S_P7_Valid,
I_Ready => S_P7_Ready
);
I_P7_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P7_InBufferEnable,
I_Data => I_P7_Data,
O_Data => S_P7_Data
);
I_PriorityEncoder_8 : entity work.PriorityEncoder_8
port map(
I_Select => C_Select,
O_Code => C_Code
);
P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid)
begin
case R_SelectRotator is when "000" =>
C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid;
when "001" =>
C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid;
when "010" =>
C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid;
when "011" =>
C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
when "100" =>
C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
when "101" =>
C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid;
when "110" =>
C_Select <= S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid;
when "111" =>
C_Select <= S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid;
when others =>
C_Select <= (others => '-');
end case;
end process;
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
begin
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
end process;
P_OutMux : process (
C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_Out_Ready)
begin
S_Out_Valid <= '0';
S_P0_Ready <= '0';
S_P1_Ready <= '0';
S_P2_Ready <= '0';
S_P3_Ready <= '0';
S_P4_Ready <= '0';
S_P5_Ready <= '0';
S_P6_Ready <= '0';
S_P7_Ready <= '0';
S_Out_Data <= (others => '-');
S_Out_Address <= C_CodeUnrotated;
case C_CodeUnrotated is when "000" =>
S_Out_Valid <= S_P0_Valid;
S_P0_Ready <= S_Out_Ready;
S_Out_Data <= S_P0_Data;
when "001" =>
S_Out_Valid <= S_P1_Valid;
S_P1_Ready <= S_Out_Ready;
S_Out_Data <= S_P1_Data;
when "010" =>
S_Out_Valid <= S_P2_Valid;
S_P2_Ready <= S_Out_Ready;
S_Out_Data <= S_P2_Data;
when "011" =>
S_Out_Valid <= S_P3_Valid;
S_P3_Ready <= S_Out_Ready;
S_Out_Data <= S_P3_Data;
when "100" =>
S_Out_Valid <= S_P4_Valid;
S_P4_Ready <= S_Out_Ready;
S_Out_Data <= S_P4_Data;
when "101" =>
S_Out_Valid <= S_P5_Valid;
S_P5_Ready <= S_Out_Ready;
S_Out_Data <= S_P5_Data;
when "110" =>
S_Out_Valid <= S_P6_Valid;
S_P6_Ready <= S_Out_Ready;
S_Out_Data <= S_P6_Data;
when "111" =>
S_Out_Valid <= S_P7_Valid;
S_P7_Ready <= S_Out_Ready;
S_Out_Data <= S_P7_Data;
when others =>
S_Out_Address <= (others => '-');
end case;
end process;
P_SelectRotator : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_CE = '1' then
if I_RST = '1' then
R_SelectRotator <= (others => '0');
R1_SelectRotator <= (others => '0');
R_Code <= (others => '0');
else
R1_SelectRotator <= R_SelectRotator;
R_Code <= C_Code;
if I_Out_Ready = '1' then
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
end if;
end if;
end if;
end if;
end process P_SelectRotator;
I_OutBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_OutBufferEnable,
I_Valid => S_Out_Valid,
O_Ready => S_Out_Ready,
O_Valid => O_Out_Valid,
I_Ready => I_Out_Ready
);
I_OutDataBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Data,
O_Data => O_Out_Data
);
I_OutAddressBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => 3,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Address,
O_Data => O_Out_Address
);
end architecture;

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import math
import os
import argparse
from jinja2 import Environment, FileSystemLoader, TemplateError
# === Argument-Parser ===
def parse_args():
parser = argparse.ArgumentParser(
description="Generiert ein VHDL-Modul für einen AXI Handshaking Scheduler mit einer wählbaren Anzahl an Ports (nur 2^n bis max. 64 erlaubt)."
)
parser.add_argument(
"--ports", "-p",
type=int,
required=True,
help="Anzahl der Ports (z. B. 2, 4, 8, 16, 32, 64)"
)
return parser.parse_args()
# === Validierung ===
def is_power_of_two(n):
return n > 0 and (n & (n - 1)) == 0
def validate_ports(n):
if not is_power_of_two(n) or n > 64:
raise ValueError("❌ Fehler: --ports muss eine Zweierpotenz ≤ 64 sein (z. B. 2, 4, 8, 16, 32, 64).")
# === Main ===
def main():
args = parse_args()
num_ports = args.ports
validate_ports(num_ports)
TEMPLATE_DIR = "./template"
TEMPLATE_FILE = "AXI-HS-Scheduler_n.vhd.j2"
OUTPUT_DIR = "./build"
env = Environment(
loader=FileSystemLoader(TEMPLATE_DIR),
trim_blocks=True,
lstrip_blocks=True
)
template = env.get_template(TEMPLATE_FILE)
rendered = template.render(num_ports=num_ports)
os.makedirs(OUTPUT_DIR, exist_ok=True)
outfile = os.path.join(OUTPUT_DIR, f"AXI_Handshaking_Scheduler_{num_ports}.vhdl")
with open(outfile, "w") as f:
f.write(rendered)
print(f"✔️ Generiert: {outfile}")
if __name__ == "__main__":
main()

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library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (2 to 1 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 1-bit output code.
entity PriorityEncoder_2 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(1 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(0 downto 0) := (others => '0')
);
end entity PriorityEncoder_2;
architecture Combinatoric of PriorityEncoder_2 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(0 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "0" when I_Select(1) = '1' else
"1" when I_Select(0) = '1' else
"-";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (4 to 2 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 2-bit output code.
entity PriorityEncoder_4 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(3 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(1 downto 0) := (others => '0')
);
end entity PriorityEncoder_4;
architecture Combinatoric of PriorityEncoder_4 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(1 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "00" when I_Select(3) = '1' else
"01" when I_Select(2) = '1' else
"10" when I_Select(1) = '1' else
"11" when I_Select(0) = '1' else
"--";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (8 to 3 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 3-bit output code.
entity PriorityEncoder_8 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(7 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(2 downto 0) := (others => '0')
);
end entity PriorityEncoder_8;
architecture Combinatoric of PriorityEncoder_8 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(2 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "000" when I_Select(7) = '1' else
"001" when I_Select(6) = '1' else
"010" when I_Select(5) = '1' else
"011" when I_Select(4) = '1' else
"100" when I_Select(3) = '1' else
"101" when I_Select(2) = '1' else
"110" when I_Select(1) = '1' else
"111" when I_Select(0) = '1' else
"---";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (16 to 4 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 4-bit output code.
entity PriorityEncoder_16 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(15 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(3 downto 0) := (others => '0')
);
end entity PriorityEncoder_16;
architecture Combinatoric of PriorityEncoder_16 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(3 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "0000" when I_Select(15) = '1' else
"0001" when I_Select(14) = '1' else
"0010" when I_Select(13) = '1' else
"0011" when I_Select(12) = '1' else
"0100" when I_Select(11) = '1' else
"0101" when I_Select(10) = '1' else
"0110" when I_Select(9) = '1' else
"0111" when I_Select(8) = '1' else
"1000" when I_Select(7) = '1' else
"1001" when I_Select(6) = '1' else
"1010" when I_Select(5) = '1' else
"1011" when I_Select(4) = '1' else
"1100" when I_Select(3) = '1' else
"1101" when I_Select(2) = '1' else
"1110" when I_Select(1) = '1' else
"1111" when I_Select(0) = '1' else
"----";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (32 to 5 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 5-bit output code.
entity PriorityEncoder_32 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(31 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(4 downto 0) := (others => '0')
);
end entity PriorityEncoder_32;
architecture Combinatoric of PriorityEncoder_32 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(4 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "00000" when I_Select(31) = '1' else
"00001" when I_Select(30) = '1' else
"00010" when I_Select(29) = '1' else
"00011" when I_Select(28) = '1' else
"00100" when I_Select(27) = '1' else
"00101" when I_Select(26) = '1' else
"00110" when I_Select(25) = '1' else
"00111" when I_Select(24) = '1' else
"01000" when I_Select(23) = '1' else
"01001" when I_Select(22) = '1' else
"01010" when I_Select(21) = '1' else
"01011" when I_Select(20) = '1' else
"01100" when I_Select(19) = '1' else
"01101" when I_Select(18) = '1' else
"01110" when I_Select(17) = '1' else
"01111" when I_Select(16) = '1' else
"10000" when I_Select(15) = '1' else
"10001" when I_Select(14) = '1' else
"10010" when I_Select(13) = '1' else
"10011" when I_Select(12) = '1' else
"10100" when I_Select(11) = '1' else
"10101" when I_Select(10) = '1' else
"10110" when I_Select(9) = '1' else
"10111" when I_Select(8) = '1' else
"11000" when I_Select(7) = '1' else
"11001" when I_Select(6) = '1' else
"11010" when I_Select(5) = '1' else
"11011" when I_Select(4) = '1' else
"11100" when I_Select(3) = '1' else
"11101" when I_Select(2) = '1' else
"11110" when I_Select(1) = '1' else
"11111" when I_Select(0) = '1' else
"-----";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--@ Priority Encoder (64 to 6 bits)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 6-bit output code.
entity PriorityEncoder_64 is
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(63 downto 0) := (others => '0');
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(5 downto 0) := (others => '0')
);
end entity PriorityEncoder_64;
architecture Combinatoric of PriorityEncoder_64 is
--@ Internal signal to hold the encoded output.
signal C_Code : std_logic_vector(5 downto 0);
--@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal.
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of C_Code : signal is "force";
begin
C_Code <= "000000" when I_Select(63) = '1' else
"000001" when I_Select(62) = '1' else
"000010" when I_Select(61) = '1' else
"000011" when I_Select(60) = '1' else
"000100" when I_Select(59) = '1' else
"000101" when I_Select(58) = '1' else
"000110" when I_Select(57) = '1' else
"000111" when I_Select(56) = '1' else
"001000" when I_Select(55) = '1' else
"001001" when I_Select(54) = '1' else
"001010" when I_Select(53) = '1' else
"001011" when I_Select(52) = '1' else
"001100" when I_Select(51) = '1' else
"001101" when I_Select(50) = '1' else
"001110" when I_Select(49) = '1' else
"001111" when I_Select(48) = '1' else
"010000" when I_Select(47) = '1' else
"010001" when I_Select(46) = '1' else
"010010" when I_Select(45) = '1' else
"010011" when I_Select(44) = '1' else
"010100" when I_Select(43) = '1' else
"010101" when I_Select(42) = '1' else
"010110" when I_Select(41) = '1' else
"010111" when I_Select(40) = '1' else
"011000" when I_Select(39) = '1' else
"011001" when I_Select(38) = '1' else
"011010" when I_Select(37) = '1' else
"011011" when I_Select(36) = '1' else
"011100" when I_Select(35) = '1' else
"011101" when I_Select(34) = '1' else
"011110" when I_Select(33) = '1' else
"011111" when I_Select(32) = '1' else
"100000" when I_Select(31) = '1' else
"100001" when I_Select(30) = '1' else
"100010" when I_Select(29) = '1' else
"100011" when I_Select(28) = '1' else
"100100" when I_Select(27) = '1' else
"100101" when I_Select(26) = '1' else
"100110" when I_Select(25) = '1' else
"100111" when I_Select(24) = '1' else
"101000" when I_Select(23) = '1' else
"101001" when I_Select(22) = '1' else
"101010" when I_Select(21) = '1' else
"101011" when I_Select(20) = '1' else
"101100" when I_Select(19) = '1' else
"101101" when I_Select(18) = '1' else
"101110" when I_Select(17) = '1' else
"101111" when I_Select(16) = '1' else
"110000" when I_Select(15) = '1' else
"110001" when I_Select(14) = '1' else
"110010" when I_Select(13) = '1' else
"110011" when I_Select(12) = '1' else
"110100" when I_Select(11) = '1' else
"110101" when I_Select(10) = '1' else
"110110" when I_Select(9) = '1' else
"110111" when I_Select(8) = '1' else
"111000" when I_Select(7) = '1' else
"111001" when I_Select(6) = '1' else
"111010" when I_Select(5) = '1' else
"111011" when I_Select(4) = '1' else
"111100" when I_Select(3) = '1' else
"111101" when I_Select(2) = '1' else
"111110" when I_Select(1) = '1' else
"111111" when I_Select(0) = '1' else
"------";
O_Code <= C_Code;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--@ Priority Encoder (Generic)
--@ This is a combinatorial priority encoder that encodes the highest priority
--@ bit in the input vector to a 6-bit output code.
entity PriorityEncoder_G is
generic (
--@ Code width with minimum 2 bits and maximum 6 bits.
G_CodeWidth : integer := 6
);
port (
--@ Input vector to be encoded.
--@ The most significant bit has the highest priority.
I_Select : in std_logic_vector(2 ** G_CodeWidth - 1 downto 0);
--@ Output code.
--@ The output code is the index of the highest priority bit in the input vector.
O_Code : out std_logic_vector(G_CodeWidth - 1 downto 0)
);
end entity PriorityEncoder_G;
architecture Combinatoric of PriorityEncoder_G is
signal C_Select : std_logic_vector(63 downto 0) := (others => '-');
signal C_Code : std_logic_vector(5 downto 0) := (others => '-');
begin
entity_inst : entity work.PriorityEncoder_64
port map(
I_Select => C_Select,
O_Code => C_Code
);
C_Select(G_CodeWidth * 2 - 1 downto 0) <= I_Select;
O_Code <= C_Code(G_CodeWidth - 1 downto 0);
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.env.stop;
entity Scheduler_tb is
end entity Scheduler_tb;
architecture Bench of Scheduler_tb is
-- Clock period
constant K_CLKPeriod : time := 10 ns;
-- Generics
constant G_DataWidth : integer := 32;
-- Ports
signal I_CLK : std_logic;
signal I_CE : std_logic := '1';
signal I_RST : std_logic := '0';
signal I_P0_Valid : std_logic := '0';
signal O_P0_Ready : std_logic := '0';
signal I_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal I_P1_Valid : std_logic := '0';
signal O_P1_Ready : std_logic := '0';
signal I_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal I_P2_Valid : std_logic := '0';
signal O_P2_Ready : std_logic := '0';
signal I_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal I_P3_Valid : std_logic := '0';
signal O_P3_Ready : std_logic := '0';
signal I_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal O_Out_Valid : std_logic := '0';
signal I_Out_Ready : std_logic := '0';
signal O_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal O_Out_Address : std_logic_vector(1 downto 0) := (others => '0');
signal TestDone : boolean := false;
begin
ClockProc : process
begin
while TestDone = false loop
I_CLK <= '0';
wait for K_CLKPeriod / 2;
I_CLK <= '1';
wait for K_CLKPeriod / 2;
end loop;
I_CLK <= '0';
stop(0);
wait;
end process;
i_AXI_Handshaking_Scheduler_4 : entity work.AXI_Handshaking_Scheduler_4
generic map(
G_DataWidth => G_DataWidth
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
I_P0_Valid => I_P0_Valid,
O_P0_Ready => O_P0_Ready,
I_P0_Data => I_P0_Data,
I_P1_Valid => I_P1_Valid,
O_P1_Ready => O_P1_Ready,
I_P1_Data => I_P1_Data,
I_P2_Valid => I_P2_Valid,
O_P2_Ready => O_P2_Ready,
I_P2_Data => I_P2_Data,
I_P3_Valid => I_P3_Valid,
O_P3_Ready => O_P3_Ready,
I_P3_Data => I_P3_Data,
O_Out_Valid => O_Out_Valid,
I_Out_Ready => I_Out_Ready,
O_Out_Data => O_Out_Data,
O_Out_Address => O_Out_Address
);
ReceiverProc : process
variable PacketCounter : integer := 0;
begin
I_Out_Ready <= '0';
wait for 3 * K_CLKPeriod;
loop
-- Ein paar Takte Ready aktivieren
I_Out_Ready <= '1';
for i in 0 to 2 loop
wait until rising_edge(I_CLK);
if O_Out_Valid = '1' and I_Out_Ready = '1' then
report "Received packet #" & integer'image(PacketCounter) &
" from address " & integer'image(to_integer(unsigned(O_Out_Address))) &
" with data: " & integer'image(to_integer(unsigned(O_Out_Data)));
PacketCounter := PacketCounter + 1;
end if;
end loop;
-- Pausephase
-- I_Out_Ready <= '0';
-- wait for 1 * K_CLKPeriod;
end loop;
end process;
-- Sender 0: sendet 1 Paket
Sender0Proc : process (I_CLK)
constant K_MaxCount : integer := 280;
variable V_Counter : integer := 0;
begin
if rising_edge(I_CLK) then
if V_Counter < K_MaxCount then
I_P0_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
I_P0_Valid <= '1';
if O_P0_Ready = '1' and I_P0_Valid = '1' then
report "Sender 0: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P0_Data)));
V_Counter := V_Counter + 1;
if V_Counter = K_MaxCount then
I_P0_Valid <= '0';
end if;
end if;
else
if V_Counter = K_MaxCount then
V_Counter := V_Counter + 1;
report "Sender 0: No more packets to send.";
end if;
I_P0_Valid <= '0';
end if;
end if;
end process;
-- Sender 1: sendet 1 Paket
Sender1Proc : process (I_CLK)
constant K_MaxCount : integer := 225;
variable V_Counter : integer := 0;
begin
if rising_edge(I_CLK) then
if V_Counter < K_MaxCount then
I_P1_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
I_P1_Valid <= '1';
if O_P1_Ready = '1' and I_P1_Valid = '1' then
report "Sender 1: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P1_Data)));
V_Counter := V_Counter + 1;
if V_Counter = K_MaxCount then
I_P1_Valid <= '0';
end if;
end if;
else
if V_Counter = K_MaxCount then
V_Counter := V_Counter + 1;
report "Sender 1: No more packets to send.";
end if;
I_P1_Valid <= '0';
end if;
end if;
end process;
-- Sender 2: sendet 1 Paket
Sender2Proc : process (I_CLK)
constant K_MaxCount : integer := 665;
variable V_Counter : integer := 0;
begin
if rising_edge(I_CLK) then
if V_Counter < K_MaxCount then
I_P2_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
I_P2_Valid <= '1';
if O_P2_Ready = '1' and I_P2_Valid = '1' then
report "Sender 2: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P2_Data)));
V_Counter := V_Counter + 1;
if V_Counter = K_MaxCount then
I_P2_Valid <= '0';
end if;
end if;
else
if V_Counter = K_MaxCount then
V_Counter := V_Counter + 1;
report "Sender 2: No more packets to send.";
end if;
I_P2_Valid <= '0';
end if;
end if;
end process;
-- Sender 3: sendet 1 Paket
Sender3Proc : process (I_CLK)
constant K_MaxCount : integer := 150;
variable V_Counter : integer := 0;
begin
if rising_edge(I_CLK) then
if V_Counter < K_MaxCount then
I_P3_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
I_P3_Valid <= '1';
if O_P3_Ready = '1' and I_P3_Valid = '1' then
report "Sender 3: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P3_Data)));
V_Counter := V_Counter + 1;
if V_Counter = K_MaxCount then
I_P3_Valid <= '0';
end if;
end if;
else
if V_Counter = K_MaxCount then
V_Counter := V_Counter + 1;
report "Sender 3: No more packets to send.";
end if;
I_P3_Valid <= '0';
end if;
end if;
end process;
end architecture;

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="env" />
<top_module name="glbl" />
<top_module name="math_real" />
<top_module name="numeric_std" />
<top_module name="scheduler_tb" />
<top_module name="std_logic_1164" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="21" />
<wvobject fp_name="/scheduler_tb/i_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_clk</obj_property>
<obj_property name="ObjectShortName">i_clk</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_ce" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_ce</obj_property>
<obj_property name="ObjectShortName">i_ce</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_rst</obj_property>
<obj_property name="ObjectShortName">i_rst</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p0_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_p0_valid</obj_property>
<obj_property name="ObjectShortName">i_p0_valid</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_p0_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_p0_ready</obj_property>
<obj_property name="ObjectShortName">o_p0_ready</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p0_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_p0_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_p0_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p1_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_p1_valid</obj_property>
<obj_property name="ObjectShortName">i_p1_valid</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_p1_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_p1_ready</obj_property>
<obj_property name="ObjectShortName">o_p1_ready</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p1_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_p1_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_p1_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p2_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_p2_valid</obj_property>
<obj_property name="ObjectShortName">i_p2_valid</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_p2_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_p2_ready</obj_property>
<obj_property name="ObjectShortName">o_p2_ready</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p2_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_p2_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_p2_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p3_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_p3_valid</obj_property>
<obj_property name="ObjectShortName">i_p3_valid</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_p3_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_p3_ready</obj_property>
<obj_property name="ObjectShortName">o_p3_ready</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_p3_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_p3_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_p3_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_out_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_out_valid</obj_property>
<obj_property name="ObjectShortName">o_out_valid</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_out_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_out_ready</obj_property>
<obj_property name="ObjectShortName">i_out_ready</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">o_out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/o_out_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_out_address[1:0]</obj_property>
<obj_property name="ObjectShortName">o_out_address[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="group29" type="group">
<obj_property name="label">Intern</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/r_counter" type="array" db_ref_id="1">
<obj_property name="ElementShortName">r_counter[1:0]</obj_property>
<obj_property name="ObjectShortName">r_counter[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/c_select" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_select[3:0]</obj_property>
<obj_property name="ObjectShortName">c_select[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/c_code" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_code[1:0]</obj_property>
<obj_property name="ObjectShortName">c_code[1:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/c_codereverse" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_codereverse[1:0]</obj_property>
<obj_property name="ObjectShortName">c_codereverse[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group30" type="group">
<obj_property name="label">PE</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/i_PriorityEncoder_4/i_select" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_select[3:0]</obj_property>
<obj_property name="ObjectShortName">i_select[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/i_PriorityEncoder_4/o_code" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_code[1:0]</obj_property>
<obj_property name="ObjectShortName">o_code[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/scheduler_tb/i_AXI_Handshaking_Scheduler_4/i_PriorityEncoder_4/c_code" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c_code[1:0]</obj_property>
<obj_property name="ObjectShortName">c_code[1:0]</obj_property>
</wvobject>
</wvobject>
</wave_config>

202
template/AXI-HS-Scheduler_n.vhd.j2 Normal file
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{% set addr_width = (num_ports - 1).bit_length() %}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_Handshaking_Scheduler_{{ num_ports }} is
generic (
G_DataWidth : integer := 8;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
{% for i in range(num_ports) %}
--@ @virtualbus P{{ i }} @dir in P{{ i }} interface
I_P{{ i }}_Valid : in std_logic := '0';
O_P{{ i }}_Ready : out std_logic := '0';
I_P{{ i }}_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
--@ @end
{% endfor %}
--@ @virtualbus Out @dir out Output interface
O_Out_Valid : out std_logic := '0';
I_Out_Ready : in std_logic := '0';
O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
O_Out_Address : out std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0')
--@ @end
);
end entity AXI_Handshaking_Scheduler_{{ num_ports }};
architecture Rtl of AXI_Handshaking_Scheduler_{{ num_ports }} is
signal R_SelectRotator : unsigned({{ addr_width - 1 }} downto 0) := (others => '0');
signal R1_SelectRotator : unsigned({{ addr_width - 1 }} downto 0) := (others => '0');
signal C_Select : std_logic_vector({{ num_ports - 1 }} downto 0) := (others => '0');
signal C_Code : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0');
signal R_Code : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0');
signal C_CodeUnrotated : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0');
{% for i in range(num_ports) %}
signal S_P{{ i }}_InBufferEnable : std_logic := '0';
signal S_P{{ i }}_Ready : std_logic := '0';
signal S_P{{ i }}_Valid : std_logic := '0';
signal S_P{{ i }}_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
{% endfor %}
signal S_OutBufferEnable : std_logic := '0';
signal S_Out_Ready : std_logic := '0';
signal S_Out_Valid : std_logic := '0';
signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_Out_Address : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0');
begin
{% for i in range(num_ports) %}
I_P{{ i }}_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P{{ i }}_InBufferEnable,
I_Valid => I_P{{ i }}_Valid,
O_Ready => O_P{{ i }}_Ready,
O_Valid => S_P{{ i }}_Valid,
I_Ready => S_P{{ i }}_Ready
);
I_P{{ i }}_InBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P{{ i }}_InBufferEnable,
I_Data => I_P{{ i }}_Data,
O_Data => S_P{{ i }}_Data
);
{% endfor %}
I_PriorityEncoder_{{ num_ports }} : entity work.PriorityEncoder_{{ num_ports }}
port map(
I_Select => C_Select,
O_Code => C_Code
);
P_SelectMux : process (R_SelectRotator
{%- for i in range(num_ports) %}, S_P{{ i }}_Valid{% endfor %})
begin
case R_SelectRotator is
{%- for r in range(num_ports) %}
when "{{ '{:0{}b}'.format(r, addr_width) }}" =>
C_Select <=
{%- for i in range(num_ports) -%}
S_P{{ (i + r) % num_ports }}_Valid{% if not loop.last %} & {% endif %}
{%- endfor %};
{% endfor %}
when others =>
C_Select <= (others => '-');
end case;
end process;
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
begin
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
end process;
P_OutMux : process (
C_CodeUnrotated
{%- for i in range(num_ports) %}, S_P{{ i }}_Data{% endfor %}
{%- for i in range(num_ports) %}, S_P{{ i }}_Valid{% endfor %}
, S_Out_Ready)
begin
S_Out_Valid <= '0';
{%- for i in range(num_ports) %}
S_P{{ i }}_Ready <= '0';
{%- endfor %}
S_Out_Data <= (others => '-');
S_Out_Address <= C_CodeUnrotated;
case C_CodeUnrotated is
{%- for i in range(num_ports) %}
when "{{ '{:0{}b}'.format(i, addr_width) }}" =>
S_Out_Valid <= S_P{{ i }}_Valid;
S_P{{ i }}_Ready <= S_Out_Ready;
S_Out_Data <= S_P{{ i }}_Data;
{%- endfor %}
when others =>
S_Out_Address <= (others => '-');
end case;
end process;
P_SelectRotator : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_CE = '1' then
if I_RST = '1' then
R_SelectRotator <= (others => '0');
R1_SelectRotator <= (others => '0');
R_Code <= (others => '0');
else
R1_SelectRotator <= R_SelectRotator;
R_Code <= C_Code;
if I_Out_Ready = '1' then
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
end if;
end if;
end if;
end if;
end process P_SelectRotator;
I_OutBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_OutBufferEnable,
I_Valid => S_Out_Valid,
O_Ready => S_Out_Ready,
O_Valid => O_Out_Valid,
I_Ready => I_Out_Ready
);
I_OutDataBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Data,
O_Data => O_Out_Data
);
I_OutAddressBuffer : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => {{ addr_width }},
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_OutBufferEnable,
I_Data => S_Out_Address,
O_Data => O_Out_Address
);
end architecture;