From f98e7d56f43fcbb614afa976dd5553cc987dbcc3 Mon Sep 17 00:00:00 2001 From: "Max P." Date: Mon, 21 Apr 2025 17:29:28 +0200 Subject: [PATCH] first commit --- build/AXI_Handshaking_Scheduler_16.vhdl | 825 +++++++ build/AXI_Handshaking_Scheduler_2.vhdl | 223 ++ build/AXI_Handshaking_Scheduler_32.vhdl | 1513 ++++++++++++ build/AXI_Handshaking_Scheduler_4.vhdl | 309 +++ build/AXI_Handshaking_Scheduler_64.vhdl | 2889 +++++++++++++++++++++++ build/AXI_Handshaking_Scheduler_8.vhdl | 481 ++++ gen.py | 55 + src/PriorityEncoders.vhd | 345 +++ tb/Scheduler_tb.vhd | 210 ++ tb/Scheduler_tb.wcfg | 133 ++ template/AXI-HS-Scheduler_n.vhd.j2 | 202 ++ 11 files changed, 7185 insertions(+) create mode 100644 build/AXI_Handshaking_Scheduler_16.vhdl create mode 100644 build/AXI_Handshaking_Scheduler_2.vhdl create mode 100644 build/AXI_Handshaking_Scheduler_32.vhdl create mode 100644 build/AXI_Handshaking_Scheduler_4.vhdl create mode 100644 build/AXI_Handshaking_Scheduler_64.vhdl create mode 100644 build/AXI_Handshaking_Scheduler_8.vhdl create mode 100644 gen.py create mode 100644 src/PriorityEncoders.vhd create mode 100644 tb/Scheduler_tb.vhd create mode 100644 tb/Scheduler_tb.wcfg create mode 100644 template/AXI-HS-Scheduler_n.vhd.j2 diff --git a/build/AXI_Handshaking_Scheduler_16.vhdl b/build/AXI_Handshaking_Scheduler_16.vhdl new file mode 100644 index 0000000..dae6154 --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_16.vhdl @@ -0,0 +1,825 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_16 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P2 @dir in P2 interface + I_P2_Valid : in std_logic := '0'; + O_P2_Ready : out std_logic := '0'; + I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P3 @dir in P3 interface + I_P3_Valid : in std_logic := '0'; + O_P3_Ready : out std_logic := '0'; + I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P4 @dir in P4 interface + I_P4_Valid : in std_logic := '0'; + O_P4_Ready : out std_logic := '0'; + I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P5 @dir in P5 interface + I_P5_Valid : in std_logic := '0'; + O_P5_Ready : out std_logic := '0'; + I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P6 @dir in P6 interface + I_P6_Valid : in std_logic := '0'; + O_P6_Ready : out std_logic := '0'; + I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P7 @dir in P7 interface + I_P7_Valid : in std_logic := '0'; + O_P7_Ready : out std_logic := '0'; + I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P8 @dir in P8 interface + I_P8_Valid : in std_logic := '0'; + O_P8_Ready : out std_logic := '0'; + I_P8_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P9 @dir in P9 interface + I_P9_Valid : in std_logic := '0'; + O_P9_Ready : out std_logic := '0'; + I_P9_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P10 @dir in P10 interface + I_P10_Valid : in std_logic := '0'; + O_P10_Ready : out std_logic := '0'; + I_P10_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P11 @dir in P11 interface + I_P11_Valid : in std_logic := '0'; + O_P11_Ready : out std_logic := '0'; + I_P11_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P12 @dir in P12 interface + I_P12_Valid : in std_logic := '0'; + O_P12_Ready : out std_logic := '0'; + I_P12_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P13 @dir in P13 interface + I_P13_Valid : in std_logic := '0'; + O_P13_Ready : out std_logic := '0'; + I_P13_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P14 @dir in P14 interface + I_P14_Valid : in std_logic := '0'; + O_P14_Ready : out std_logic := '0'; + I_P14_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P15 @dir in P15 interface + I_P15_Valid : in std_logic := '0'; + O_P15_Ready : out std_logic := '0'; + I_P15_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(3 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_16; + +architecture Rtl of AXI_Handshaking_Scheduler_16 is + signal R_SelectRotator : unsigned(3 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(3 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(15 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(3 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(3 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(3 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P2_InBufferEnable : std_logic := '0'; + signal S_P2_Ready : std_logic := '0'; + signal S_P2_Valid : std_logic := '0'; + signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P3_InBufferEnable : std_logic := '0'; + signal S_P3_Ready : std_logic := '0'; + signal S_P3_Valid : std_logic := '0'; + signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P4_InBufferEnable : std_logic := '0'; + signal S_P4_Ready : std_logic := '0'; + signal S_P4_Valid : std_logic := '0'; + signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P5_InBufferEnable : std_logic := '0'; + signal S_P5_Ready : std_logic := '0'; + signal S_P5_Valid : std_logic := '0'; + signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P6_InBufferEnable : std_logic := '0'; + signal S_P6_Ready : std_logic := '0'; + signal S_P6_Valid : std_logic := '0'; + signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P7_InBufferEnable : std_logic := '0'; + signal S_P7_Ready : std_logic := '0'; + signal S_P7_Valid : std_logic := '0'; + signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P8_InBufferEnable : std_logic := '0'; + signal S_P8_Ready : std_logic := '0'; + signal S_P8_Valid : std_logic := '0'; + signal S_P8_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P9_InBufferEnable : std_logic := '0'; + signal S_P9_Ready : std_logic := '0'; + signal S_P9_Valid : std_logic := '0'; + signal S_P9_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P10_InBufferEnable : std_logic := '0'; + signal S_P10_Ready : std_logic := '0'; + signal S_P10_Valid : std_logic := '0'; + signal S_P10_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P11_InBufferEnable : std_logic := '0'; + signal S_P11_Ready : std_logic := '0'; + signal S_P11_Valid : std_logic := '0'; + signal S_P11_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P12_InBufferEnable : std_logic := '0'; + signal S_P12_Ready : std_logic := '0'; + signal S_P12_Valid : std_logic := '0'; + signal S_P12_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P13_InBufferEnable : std_logic := '0'; + signal S_P13_Ready : std_logic := '0'; + signal S_P13_Valid : std_logic := '0'; + signal S_P13_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P14_InBufferEnable : std_logic := '0'; + signal S_P14_Ready : std_logic := '0'; + signal S_P14_Valid : std_logic := '0'; + signal S_P14_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P15_InBufferEnable : std_logic := '0'; + signal S_P15_Ready : std_logic := '0'; + signal S_P15_Valid : std_logic := '0'; + signal S_P15_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(3 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + I_P2_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P2_InBufferEnable, + I_Valid => I_P2_Valid, + O_Ready => O_P2_Ready, + O_Valid => S_P2_Valid, + I_Ready => S_P2_Ready + ); + + I_P2_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P2_InBufferEnable, + I_Data => I_P2_Data, + O_Data => S_P2_Data + ); + I_P3_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P3_InBufferEnable, + I_Valid => I_P3_Valid, + O_Ready => O_P3_Ready, + O_Valid => S_P3_Valid, + I_Ready => S_P3_Ready + ); + + I_P3_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P3_InBufferEnable, + I_Data => I_P3_Data, + O_Data => S_P3_Data + ); + I_P4_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P4_InBufferEnable, + I_Valid => I_P4_Valid, + O_Ready => O_P4_Ready, + O_Valid => S_P4_Valid, + I_Ready => S_P4_Ready + ); + + I_P4_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P4_InBufferEnable, + I_Data => I_P4_Data, + O_Data => S_P4_Data + ); + I_P5_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P5_InBufferEnable, + I_Valid => I_P5_Valid, + O_Ready => O_P5_Ready, + O_Valid => S_P5_Valid, + I_Ready => S_P5_Ready + ); + + I_P5_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P5_InBufferEnable, + I_Data => I_P5_Data, + O_Data => S_P5_Data + ); + I_P6_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P6_InBufferEnable, + I_Valid => I_P6_Valid, + O_Ready => O_P6_Ready, + O_Valid => S_P6_Valid, + I_Ready => S_P6_Ready + ); + + I_P6_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P6_InBufferEnable, + I_Data => I_P6_Data, + O_Data => S_P6_Data + ); + I_P7_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P7_InBufferEnable, + I_Valid => I_P7_Valid, + O_Ready => O_P7_Ready, + O_Valid => S_P7_Valid, + I_Ready => S_P7_Ready + ); + + I_P7_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P7_InBufferEnable, + I_Data => I_P7_Data, + O_Data => S_P7_Data + ); + I_P8_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P8_InBufferEnable, + I_Valid => I_P8_Valid, + O_Ready => O_P8_Ready, + O_Valid => S_P8_Valid, + I_Ready => S_P8_Ready + ); + + I_P8_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P8_InBufferEnable, + I_Data => I_P8_Data, + O_Data => S_P8_Data + ); + I_P9_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P9_InBufferEnable, + I_Valid => I_P9_Valid, + O_Ready => O_P9_Ready, + O_Valid => S_P9_Valid, + I_Ready => S_P9_Ready + ); + + I_P9_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P9_InBufferEnable, + I_Data => I_P9_Data, + O_Data => S_P9_Data + ); + I_P10_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P10_InBufferEnable, + I_Valid => I_P10_Valid, + O_Ready => O_P10_Ready, + O_Valid => S_P10_Valid, + I_Ready => S_P10_Ready + ); + + I_P10_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P10_InBufferEnable, + I_Data => I_P10_Data, + O_Data => S_P10_Data + ); + I_P11_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P11_InBufferEnable, + I_Valid => I_P11_Valid, + O_Ready => O_P11_Ready, + O_Valid => S_P11_Valid, + I_Ready => S_P11_Ready + ); + + I_P11_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P11_InBufferEnable, + I_Data => I_P11_Data, + O_Data => S_P11_Data + ); + I_P12_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P12_InBufferEnable, + I_Valid => I_P12_Valid, + O_Ready => O_P12_Ready, + O_Valid => S_P12_Valid, + I_Ready => S_P12_Ready + ); + + I_P12_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P12_InBufferEnable, + I_Data => I_P12_Data, + O_Data => S_P12_Data + ); + I_P13_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P13_InBufferEnable, + I_Valid => I_P13_Valid, + O_Ready => O_P13_Ready, + O_Valid => S_P13_Valid, + I_Ready => S_P13_Ready + ); + + I_P13_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P13_InBufferEnable, + I_Data => I_P13_Data, + O_Data => S_P13_Data + ); + I_P14_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P14_InBufferEnable, + I_Valid => I_P14_Valid, + O_Ready => O_P14_Ready, + O_Valid => S_P14_Valid, + I_Ready => S_P14_Ready + ); + + I_P14_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P14_InBufferEnable, + I_Data => I_P14_Data, + O_Data => S_P14_Data + ); + I_P15_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P15_InBufferEnable, + I_Valid => I_P15_Valid, + O_Ready => O_P15_Ready, + O_Valid => S_P15_Valid, + I_Ready => S_P15_Ready + ); + + I_P15_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P15_InBufferEnable, + I_Data => I_P15_Data, + O_Data => S_P15_Data + ); + + I_PriorityEncoder_16 : entity work.PriorityEncoder_16 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid) + begin + case R_SelectRotator is when "0000" => + C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid; + when "0001" => + C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid; + when "0010" => + C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid; + when "0011" => + C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid; + when "0100" => + C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid; + when "0101" => + C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid; + when "0110" => + C_Select <= S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid; + when "0111" => + C_Select <= S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid; + when "1000" => + C_Select <= S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid; + when "1001" => + C_Select <= S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid; + when "1010" => + C_Select <= S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid; + when "1011" => + C_Select <= S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid; + when "1100" => + C_Select <= S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid; + when "1101" => + C_Select <= S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid; + when "1110" => + C_Select <= S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid; + when "1111" => + C_Select <= S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P8_Data, S_P9_Data, S_P10_Data, S_P11_Data, S_P12_Data, S_P13_Data, S_P14_Data, S_P15_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_P2_Ready <= '0'; + S_P3_Ready <= '0'; + S_P4_Ready <= '0'; + S_P5_Ready <= '0'; + S_P6_Ready <= '0'; + S_P7_Ready <= '0'; + S_P8_Ready <= '0'; + S_P9_Ready <= '0'; + S_P10_Ready <= '0'; + S_P11_Ready <= '0'; + S_P12_Ready <= '0'; + S_P13_Ready <= '0'; + S_P14_Ready <= '0'; + S_P15_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "0000" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "0001" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when "0010" => + S_Out_Valid <= S_P2_Valid; + S_P2_Ready <= S_Out_Ready; + S_Out_Data <= S_P2_Data; + when "0011" => + S_Out_Valid <= S_P3_Valid; + S_P3_Ready <= S_Out_Ready; + S_Out_Data <= S_P3_Data; + when "0100" => + S_Out_Valid <= S_P4_Valid; + S_P4_Ready <= S_Out_Ready; + S_Out_Data <= S_P4_Data; + when "0101" => + S_Out_Valid <= S_P5_Valid; + S_P5_Ready <= S_Out_Ready; + S_Out_Data <= S_P5_Data; + when "0110" => + S_Out_Valid <= S_P6_Valid; + S_P6_Ready <= S_Out_Ready; + S_Out_Data <= S_P6_Data; + when "0111" => + S_Out_Valid <= S_P7_Valid; + S_P7_Ready <= S_Out_Ready; + S_Out_Data <= S_P7_Data; + when "1000" => + S_Out_Valid <= S_P8_Valid; + S_P8_Ready <= S_Out_Ready; + S_Out_Data <= S_P8_Data; + when "1001" => + S_Out_Valid <= S_P9_Valid; + S_P9_Ready <= S_Out_Ready; + S_Out_Data <= S_P9_Data; + when "1010" => + S_Out_Valid <= S_P10_Valid; + S_P10_Ready <= S_Out_Ready; + S_Out_Data <= S_P10_Data; + when "1011" => + S_Out_Valid <= S_P11_Valid; + S_P11_Ready <= S_Out_Ready; + S_Out_Data <= S_P11_Data; + when "1100" => + S_Out_Valid <= S_P12_Valid; + S_P12_Ready <= S_Out_Ready; + S_Out_Data <= S_P12_Data; + when "1101" => + S_Out_Valid <= S_P13_Valid; + S_P13_Ready <= S_Out_Ready; + S_Out_Data <= S_P13_Data; + when "1110" => + S_Out_Valid <= S_P14_Valid; + S_P14_Ready <= S_Out_Ready; + S_Out_Data <= S_P14_Data; + when "1111" => + S_Out_Valid <= S_P15_Valid; + S_P15_Ready <= S_Out_Ready; + S_Out_Data <= S_P15_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 4, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/build/AXI_Handshaking_Scheduler_2.vhdl b/build/AXI_Handshaking_Scheduler_2.vhdl new file mode 100644 index 0000000..49f4d19 --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_2.vhdl @@ -0,0 +1,223 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_2 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(0 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_2; + +architecture Rtl of AXI_Handshaking_Scheduler_2 is + signal R_SelectRotator : unsigned(0 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(0 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(1 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(0 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(0 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(0 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(0 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + + I_PriorityEncoder_2 : entity work.PriorityEncoder_2 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid) + begin + case R_SelectRotator is when "0" => + C_Select <= S_P0_Valid & S_P1_Valid; + when "1" => + C_Select <= S_P1_Valid & S_P0_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P0_Valid, S_P1_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "0" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "1" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 1, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/build/AXI_Handshaking_Scheduler_32.vhdl b/build/AXI_Handshaking_Scheduler_32.vhdl new file mode 100644 index 0000000..6377af3 --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_32.vhdl @@ -0,0 +1,1513 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_32 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P2 @dir in P2 interface + I_P2_Valid : in std_logic := '0'; + O_P2_Ready : out std_logic := '0'; + I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P3 @dir in P3 interface + I_P3_Valid : in std_logic := '0'; + O_P3_Ready : out std_logic := '0'; + I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P4 @dir in P4 interface + I_P4_Valid : in std_logic := '0'; + O_P4_Ready : out std_logic := '0'; + I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P5 @dir in P5 interface + I_P5_Valid : in std_logic := '0'; + O_P5_Ready : out std_logic := '0'; + I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P6 @dir in P6 interface + I_P6_Valid : in std_logic := '0'; + O_P6_Ready : out std_logic := '0'; + I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P7 @dir in P7 interface + I_P7_Valid : in std_logic := '0'; + O_P7_Ready : out std_logic := '0'; + I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P8 @dir in P8 interface + I_P8_Valid : in std_logic := '0'; + O_P8_Ready : out std_logic := '0'; + I_P8_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P9 @dir in P9 interface + I_P9_Valid : in std_logic := '0'; + O_P9_Ready : out std_logic := '0'; + I_P9_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P10 @dir in P10 interface + I_P10_Valid : in std_logic := '0'; + O_P10_Ready : out std_logic := '0'; + I_P10_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P11 @dir in P11 interface + I_P11_Valid : in std_logic := '0'; + O_P11_Ready : out std_logic := '0'; + I_P11_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P12 @dir in P12 interface + I_P12_Valid : in std_logic := '0'; + O_P12_Ready : out std_logic := '0'; + I_P12_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P13 @dir in P13 interface + I_P13_Valid : in std_logic := '0'; + O_P13_Ready : out std_logic := '0'; + I_P13_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P14 @dir in P14 interface + I_P14_Valid : in std_logic := '0'; + O_P14_Ready : out std_logic := '0'; + I_P14_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P15 @dir in P15 interface + I_P15_Valid : in std_logic := '0'; + O_P15_Ready : out std_logic := '0'; + I_P15_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P16 @dir in P16 interface + I_P16_Valid : in std_logic := '0'; + O_P16_Ready : out std_logic := '0'; + I_P16_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P17 @dir in P17 interface + I_P17_Valid : in std_logic := '0'; + O_P17_Ready : out std_logic := '0'; + I_P17_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P18 @dir in P18 interface + I_P18_Valid : in std_logic := '0'; + O_P18_Ready : out std_logic := '0'; + I_P18_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P19 @dir in P19 interface + I_P19_Valid : in std_logic := '0'; + O_P19_Ready : out std_logic := '0'; + I_P19_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P20 @dir in P20 interface + I_P20_Valid : in std_logic := '0'; + O_P20_Ready : out std_logic := '0'; + I_P20_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P21 @dir in P21 interface + I_P21_Valid : in std_logic := '0'; + O_P21_Ready : out std_logic := '0'; + I_P21_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P22 @dir in P22 interface + I_P22_Valid : in std_logic := '0'; + O_P22_Ready : out std_logic := '0'; + I_P22_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P23 @dir in P23 interface + I_P23_Valid : in std_logic := '0'; + O_P23_Ready : out std_logic := '0'; + I_P23_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P24 @dir in P24 interface + I_P24_Valid : in std_logic := '0'; + O_P24_Ready : out std_logic := '0'; + I_P24_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P25 @dir in P25 interface + I_P25_Valid : in std_logic := '0'; + O_P25_Ready : out std_logic := '0'; + I_P25_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P26 @dir in P26 interface + I_P26_Valid : in std_logic := '0'; + O_P26_Ready : out std_logic := '0'; + I_P26_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P27 @dir in P27 interface + I_P27_Valid : in std_logic := '0'; + O_P27_Ready : out std_logic := '0'; + I_P27_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P28 @dir in P28 interface + I_P28_Valid : in std_logic := '0'; + O_P28_Ready : out std_logic := '0'; + I_P28_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P29 @dir in P29 interface + I_P29_Valid : in std_logic := '0'; + O_P29_Ready : out std_logic := '0'; + I_P29_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P30 @dir in P30 interface + I_P30_Valid : in std_logic := '0'; + O_P30_Ready : out std_logic := '0'; + I_P30_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P31 @dir in P31 interface + I_P31_Valid : in std_logic := '0'; + O_P31_Ready : out std_logic := '0'; + I_P31_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(4 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_32; + +architecture Rtl of AXI_Handshaking_Scheduler_32 is + signal R_SelectRotator : unsigned(4 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(4 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(31 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(4 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(4 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(4 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P2_InBufferEnable : std_logic := '0'; + signal S_P2_Ready : std_logic := '0'; + signal S_P2_Valid : std_logic := '0'; + signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P3_InBufferEnable : std_logic := '0'; + signal S_P3_Ready : std_logic := '0'; + signal S_P3_Valid : std_logic := '0'; + signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P4_InBufferEnable : std_logic := '0'; + signal S_P4_Ready : std_logic := '0'; + signal S_P4_Valid : std_logic := '0'; + signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P5_InBufferEnable : std_logic := '0'; + signal S_P5_Ready : std_logic := '0'; + signal S_P5_Valid : std_logic := '0'; + signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P6_InBufferEnable : std_logic := '0'; + signal S_P6_Ready : std_logic := '0'; + signal S_P6_Valid : std_logic := '0'; + signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P7_InBufferEnable : std_logic := '0'; + signal S_P7_Ready : std_logic := '0'; + signal S_P7_Valid : std_logic := '0'; + signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P8_InBufferEnable : std_logic := '0'; + signal S_P8_Ready : std_logic := '0'; + signal S_P8_Valid : std_logic := '0'; + signal S_P8_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P9_InBufferEnable : std_logic := '0'; + signal S_P9_Ready : std_logic := '0'; + signal S_P9_Valid : std_logic := '0'; + signal S_P9_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P10_InBufferEnable : std_logic := '0'; + signal S_P10_Ready : std_logic := '0'; + signal S_P10_Valid : std_logic := '0'; + signal S_P10_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P11_InBufferEnable : std_logic := '0'; + signal S_P11_Ready : std_logic := '0'; + signal S_P11_Valid : std_logic := '0'; + signal S_P11_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P12_InBufferEnable : std_logic := '0'; + signal S_P12_Ready : std_logic := '0'; + signal S_P12_Valid : std_logic := '0'; + signal S_P12_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P13_InBufferEnable : std_logic := '0'; + signal S_P13_Ready : std_logic := '0'; + signal S_P13_Valid : std_logic := '0'; + signal S_P13_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P14_InBufferEnable : std_logic := '0'; + signal S_P14_Ready : std_logic := '0'; + signal S_P14_Valid : std_logic := '0'; + signal S_P14_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P15_InBufferEnable : std_logic := '0'; + signal S_P15_Ready : std_logic := '0'; + signal S_P15_Valid : std_logic := '0'; + signal S_P15_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P16_InBufferEnable : std_logic := '0'; + signal S_P16_Ready : std_logic := '0'; + signal S_P16_Valid : std_logic := '0'; + signal S_P16_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P17_InBufferEnable : std_logic := '0'; + signal S_P17_Ready : std_logic := '0'; + signal S_P17_Valid : std_logic := '0'; + signal S_P17_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P18_InBufferEnable : std_logic := '0'; + signal S_P18_Ready : std_logic := '0'; + signal S_P18_Valid : std_logic := '0'; + signal S_P18_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P19_InBufferEnable : std_logic := '0'; + signal S_P19_Ready : std_logic := '0'; + signal S_P19_Valid : std_logic := '0'; + signal S_P19_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P20_InBufferEnable : std_logic := '0'; + signal S_P20_Ready : std_logic := '0'; + signal S_P20_Valid : std_logic := '0'; + signal S_P20_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P21_InBufferEnable : std_logic := '0'; + signal S_P21_Ready : std_logic := '0'; + signal S_P21_Valid : std_logic := '0'; + signal S_P21_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P22_InBufferEnable : std_logic := '0'; + signal S_P22_Ready : std_logic := '0'; + signal S_P22_Valid : std_logic := '0'; + signal S_P22_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P23_InBufferEnable : std_logic := '0'; + signal S_P23_Ready : std_logic := '0'; + signal S_P23_Valid : std_logic := '0'; + signal S_P23_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P24_InBufferEnable : std_logic := '0'; + signal S_P24_Ready : std_logic := '0'; + signal S_P24_Valid : std_logic := '0'; + signal S_P24_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P25_InBufferEnable : std_logic := '0'; + signal S_P25_Ready : std_logic := '0'; + signal S_P25_Valid : std_logic := '0'; + signal S_P25_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P26_InBufferEnable : std_logic := '0'; + signal S_P26_Ready : std_logic := '0'; + signal S_P26_Valid : std_logic := '0'; + signal S_P26_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P27_InBufferEnable : std_logic := '0'; + signal S_P27_Ready : std_logic := '0'; + signal S_P27_Valid : std_logic := '0'; + signal S_P27_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P28_InBufferEnable : std_logic := '0'; + signal S_P28_Ready : std_logic := '0'; + signal S_P28_Valid : std_logic := '0'; + signal S_P28_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P29_InBufferEnable : std_logic := '0'; + signal S_P29_Ready : std_logic := '0'; + signal S_P29_Valid : std_logic := '0'; + signal S_P29_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P30_InBufferEnable : std_logic := '0'; + signal S_P30_Ready : std_logic := '0'; + signal S_P30_Valid : std_logic := '0'; + signal S_P30_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P31_InBufferEnable : std_logic := '0'; + signal S_P31_Ready : std_logic := '0'; + signal S_P31_Valid : std_logic := '0'; + signal S_P31_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(4 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + I_P2_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P2_InBufferEnable, + I_Valid => I_P2_Valid, + O_Ready => O_P2_Ready, + O_Valid => S_P2_Valid, + I_Ready => S_P2_Ready + ); + + I_P2_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P2_InBufferEnable, + I_Data => I_P2_Data, + O_Data => S_P2_Data + ); + I_P3_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P3_InBufferEnable, + I_Valid => I_P3_Valid, + O_Ready => O_P3_Ready, + O_Valid => S_P3_Valid, + I_Ready => S_P3_Ready + ); + + I_P3_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P3_InBufferEnable, + I_Data => I_P3_Data, + O_Data => S_P3_Data + ); + I_P4_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P4_InBufferEnable, + I_Valid => I_P4_Valid, + O_Ready => O_P4_Ready, + O_Valid => S_P4_Valid, + I_Ready => S_P4_Ready + ); + + I_P4_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P4_InBufferEnable, + I_Data => I_P4_Data, + O_Data => S_P4_Data + ); + I_P5_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P5_InBufferEnable, + I_Valid => I_P5_Valid, + O_Ready => O_P5_Ready, + O_Valid => S_P5_Valid, + I_Ready => S_P5_Ready + ); + + I_P5_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P5_InBufferEnable, + I_Data => I_P5_Data, + O_Data => S_P5_Data + ); + I_P6_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P6_InBufferEnable, + I_Valid => I_P6_Valid, + O_Ready => O_P6_Ready, + O_Valid => S_P6_Valid, + I_Ready => S_P6_Ready + ); + + I_P6_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P6_InBufferEnable, + I_Data => I_P6_Data, + O_Data => S_P6_Data + ); + I_P7_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P7_InBufferEnable, + I_Valid => I_P7_Valid, + O_Ready => O_P7_Ready, + O_Valid => S_P7_Valid, + I_Ready => S_P7_Ready + ); + + I_P7_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P7_InBufferEnable, + I_Data => I_P7_Data, + O_Data => S_P7_Data + ); + I_P8_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P8_InBufferEnable, + I_Valid => I_P8_Valid, + O_Ready => O_P8_Ready, + O_Valid => S_P8_Valid, + I_Ready => S_P8_Ready + ); + + I_P8_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P8_InBufferEnable, + I_Data => I_P8_Data, + O_Data => S_P8_Data + ); + I_P9_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P9_InBufferEnable, + I_Valid => I_P9_Valid, + O_Ready => O_P9_Ready, + O_Valid => S_P9_Valid, + I_Ready => S_P9_Ready + ); + + I_P9_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P9_InBufferEnable, + I_Data => I_P9_Data, + O_Data => S_P9_Data + ); + I_P10_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P10_InBufferEnable, + I_Valid => I_P10_Valid, + O_Ready => O_P10_Ready, + O_Valid => S_P10_Valid, + I_Ready => S_P10_Ready + ); + + I_P10_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P10_InBufferEnable, + I_Data => I_P10_Data, + O_Data => S_P10_Data + ); + I_P11_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P11_InBufferEnable, + I_Valid => I_P11_Valid, + O_Ready => O_P11_Ready, + O_Valid => S_P11_Valid, + I_Ready => S_P11_Ready + ); + + I_P11_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P11_InBufferEnable, + I_Data => I_P11_Data, + O_Data => S_P11_Data + ); + I_P12_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P12_InBufferEnable, + I_Valid => I_P12_Valid, + O_Ready => O_P12_Ready, + O_Valid => S_P12_Valid, + I_Ready => S_P12_Ready + ); + + I_P12_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P12_InBufferEnable, + I_Data => I_P12_Data, + O_Data => S_P12_Data + ); + I_P13_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P13_InBufferEnable, + I_Valid => I_P13_Valid, + O_Ready => O_P13_Ready, + O_Valid => S_P13_Valid, + I_Ready => S_P13_Ready + ); + + I_P13_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P13_InBufferEnable, + I_Data => I_P13_Data, + O_Data => S_P13_Data + ); + I_P14_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P14_InBufferEnable, + I_Valid => I_P14_Valid, + O_Ready => O_P14_Ready, + O_Valid => S_P14_Valid, + I_Ready => S_P14_Ready + ); + + I_P14_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P14_InBufferEnable, + I_Data => I_P14_Data, + O_Data => S_P14_Data + ); + I_P15_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P15_InBufferEnable, + I_Valid => I_P15_Valid, + O_Ready => O_P15_Ready, + O_Valid => S_P15_Valid, + I_Ready => S_P15_Ready + ); + + I_P15_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P15_InBufferEnable, + I_Data => I_P15_Data, + O_Data => S_P15_Data + ); + I_P16_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P16_InBufferEnable, + I_Valid => I_P16_Valid, + O_Ready => O_P16_Ready, + O_Valid => S_P16_Valid, + I_Ready => S_P16_Ready + ); + + I_P16_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P16_InBufferEnable, + I_Data => I_P16_Data, + O_Data => S_P16_Data + ); + I_P17_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P17_InBufferEnable, + I_Valid => I_P17_Valid, + O_Ready => O_P17_Ready, + O_Valid => S_P17_Valid, + I_Ready => S_P17_Ready + ); + + I_P17_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P17_InBufferEnable, + I_Data => I_P17_Data, + O_Data => S_P17_Data + ); + I_P18_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P18_InBufferEnable, + I_Valid => I_P18_Valid, + O_Ready => O_P18_Ready, + O_Valid => S_P18_Valid, + I_Ready => S_P18_Ready + ); + + I_P18_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P18_InBufferEnable, + I_Data => I_P18_Data, + O_Data => S_P18_Data + ); + I_P19_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P19_InBufferEnable, + I_Valid => I_P19_Valid, + O_Ready => O_P19_Ready, + O_Valid => S_P19_Valid, + I_Ready => S_P19_Ready + ); + + I_P19_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P19_InBufferEnable, + I_Data => I_P19_Data, + O_Data => S_P19_Data + ); + I_P20_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P20_InBufferEnable, + I_Valid => I_P20_Valid, + O_Ready => O_P20_Ready, + O_Valid => S_P20_Valid, + I_Ready => S_P20_Ready + ); + + I_P20_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P20_InBufferEnable, + I_Data => I_P20_Data, + O_Data => S_P20_Data + ); + I_P21_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P21_InBufferEnable, + I_Valid => I_P21_Valid, + O_Ready => O_P21_Ready, + O_Valid => S_P21_Valid, + I_Ready => S_P21_Ready + ); + + I_P21_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P21_InBufferEnable, + I_Data => I_P21_Data, + O_Data => S_P21_Data + ); + I_P22_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P22_InBufferEnable, + I_Valid => I_P22_Valid, + O_Ready => O_P22_Ready, + O_Valid => S_P22_Valid, + I_Ready => S_P22_Ready + ); + + I_P22_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P22_InBufferEnable, + I_Data => I_P22_Data, + O_Data => S_P22_Data + ); + I_P23_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P23_InBufferEnable, + I_Valid => I_P23_Valid, + O_Ready => O_P23_Ready, + O_Valid => S_P23_Valid, + I_Ready => S_P23_Ready + ); + + I_P23_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P23_InBufferEnable, + I_Data => I_P23_Data, + O_Data => S_P23_Data + ); + I_P24_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P24_InBufferEnable, + I_Valid => I_P24_Valid, + O_Ready => O_P24_Ready, + O_Valid => S_P24_Valid, + I_Ready => S_P24_Ready + ); + + I_P24_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P24_InBufferEnable, + I_Data => I_P24_Data, + O_Data => S_P24_Data + ); + I_P25_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P25_InBufferEnable, + I_Valid => I_P25_Valid, + O_Ready => O_P25_Ready, + O_Valid => S_P25_Valid, + I_Ready => S_P25_Ready + ); + + I_P25_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P25_InBufferEnable, + I_Data => I_P25_Data, + O_Data => S_P25_Data + ); + I_P26_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P26_InBufferEnable, + I_Valid => I_P26_Valid, + O_Ready => O_P26_Ready, + O_Valid => S_P26_Valid, + I_Ready => S_P26_Ready + ); + + I_P26_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P26_InBufferEnable, + I_Data => I_P26_Data, + O_Data => S_P26_Data + ); + I_P27_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P27_InBufferEnable, + I_Valid => I_P27_Valid, + O_Ready => O_P27_Ready, + O_Valid => S_P27_Valid, + I_Ready => S_P27_Ready + ); + + I_P27_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P27_InBufferEnable, + I_Data => I_P27_Data, + O_Data => S_P27_Data + ); + I_P28_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P28_InBufferEnable, + I_Valid => I_P28_Valid, + O_Ready => O_P28_Ready, + O_Valid => S_P28_Valid, + I_Ready => S_P28_Ready + ); + + I_P28_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P28_InBufferEnable, + I_Data => I_P28_Data, + O_Data => S_P28_Data + ); + I_P29_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P29_InBufferEnable, + I_Valid => I_P29_Valid, + O_Ready => O_P29_Ready, + O_Valid => S_P29_Valid, + I_Ready => S_P29_Ready + ); + + I_P29_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P29_InBufferEnable, + I_Data => I_P29_Data, + O_Data => S_P29_Data + ); + I_P30_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P30_InBufferEnable, + I_Valid => I_P30_Valid, + O_Ready => O_P30_Ready, + O_Valid => S_P30_Valid, + I_Ready => S_P30_Ready + ); + + I_P30_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P30_InBufferEnable, + I_Data => I_P30_Data, + O_Data => S_P30_Data + ); + I_P31_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P31_InBufferEnable, + I_Valid => I_P31_Valid, + O_Ready => O_P31_Ready, + O_Valid => S_P31_Valid, + I_Ready => S_P31_Ready + ); + + I_P31_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P31_InBufferEnable, + I_Data => I_P31_Data, + O_Data => S_P31_Data + ); + + I_PriorityEncoder_32 : entity work.PriorityEncoder_32 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_P16_Valid, S_P17_Valid, S_P18_Valid, S_P19_Valid, S_P20_Valid, S_P21_Valid, S_P22_Valid, S_P23_Valid, S_P24_Valid, S_P25_Valid, S_P26_Valid, S_P27_Valid, S_P28_Valid, S_P29_Valid, S_P30_Valid, S_P31_Valid) + begin + case R_SelectRotator is when "00000" => + C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid; + when "00001" => + C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid; + when "00010" => + C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid; + when "00011" => + C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid; + when "00100" => + C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid; + when "00101" => + C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid; + when "00110" => + C_Select <= S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid; + when "00111" => + C_Select <= S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid; + when "01000" => + C_Select <= S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid; + when "01001" => + C_Select <= S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid; + when "01010" => + C_Select <= S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid; + when "01011" => + C_Select <= S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid; + when "01100" => + C_Select <= S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid; + when "01101" => + C_Select <= S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid; + when "01110" => + C_Select <= S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid; + when "01111" => + C_Select <= S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid; + when "10000" => + C_Select <= S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid; + when "10001" => + C_Select <= S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid; + when "10010" => + C_Select <= S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid; + when "10011" => + C_Select <= S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid; + when "10100" => + C_Select <= S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid; + when "10101" => + C_Select <= S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid; + when "10110" => + C_Select <= S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid; + when "10111" => + C_Select <= S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid; + when "11000" => + C_Select <= S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid; + when "11001" => + C_Select <= S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid; + when "11010" => + C_Select <= S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid; + when "11011" => + C_Select <= S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid; + when "11100" => + C_Select <= S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid; + when "11101" => + C_Select <= S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid; + when "11110" => + C_Select <= S_P30_Valid & S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid; + when "11111" => + C_Select <= S_P31_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P8_Data, S_P9_Data, S_P10_Data, S_P11_Data, S_P12_Data, S_P13_Data, S_P14_Data, S_P15_Data, S_P16_Data, S_P17_Data, S_P18_Data, S_P19_Data, S_P20_Data, S_P21_Data, S_P22_Data, S_P23_Data, S_P24_Data, S_P25_Data, S_P26_Data, S_P27_Data, S_P28_Data, S_P29_Data, S_P30_Data, S_P31_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_P16_Valid, S_P17_Valid, S_P18_Valid, S_P19_Valid, S_P20_Valid, S_P21_Valid, S_P22_Valid, S_P23_Valid, S_P24_Valid, S_P25_Valid, S_P26_Valid, S_P27_Valid, S_P28_Valid, S_P29_Valid, S_P30_Valid, S_P31_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_P2_Ready <= '0'; + S_P3_Ready <= '0'; + S_P4_Ready <= '0'; + S_P5_Ready <= '0'; + S_P6_Ready <= '0'; + S_P7_Ready <= '0'; + S_P8_Ready <= '0'; + S_P9_Ready <= '0'; + S_P10_Ready <= '0'; + S_P11_Ready <= '0'; + S_P12_Ready <= '0'; + S_P13_Ready <= '0'; + S_P14_Ready <= '0'; + S_P15_Ready <= '0'; + S_P16_Ready <= '0'; + S_P17_Ready <= '0'; + S_P18_Ready <= '0'; + S_P19_Ready <= '0'; + S_P20_Ready <= '0'; + S_P21_Ready <= '0'; + S_P22_Ready <= '0'; + S_P23_Ready <= '0'; + S_P24_Ready <= '0'; + S_P25_Ready <= '0'; + S_P26_Ready <= '0'; + S_P27_Ready <= '0'; + S_P28_Ready <= '0'; + S_P29_Ready <= '0'; + S_P30_Ready <= '0'; + S_P31_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "00000" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "00001" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when "00010" => + S_Out_Valid <= S_P2_Valid; + S_P2_Ready <= S_Out_Ready; + S_Out_Data <= S_P2_Data; + when "00011" => + S_Out_Valid <= S_P3_Valid; + S_P3_Ready <= S_Out_Ready; + S_Out_Data <= S_P3_Data; + when "00100" => + S_Out_Valid <= S_P4_Valid; + S_P4_Ready <= S_Out_Ready; + S_Out_Data <= S_P4_Data; + when "00101" => + S_Out_Valid <= S_P5_Valid; + S_P5_Ready <= S_Out_Ready; + S_Out_Data <= S_P5_Data; + when "00110" => + S_Out_Valid <= S_P6_Valid; + S_P6_Ready <= S_Out_Ready; + S_Out_Data <= S_P6_Data; + when "00111" => + S_Out_Valid <= S_P7_Valid; + S_P7_Ready <= S_Out_Ready; + S_Out_Data <= S_P7_Data; + when "01000" => + S_Out_Valid <= S_P8_Valid; + S_P8_Ready <= S_Out_Ready; + S_Out_Data <= S_P8_Data; + when "01001" => + S_Out_Valid <= S_P9_Valid; + S_P9_Ready <= S_Out_Ready; + S_Out_Data <= S_P9_Data; + when "01010" => + S_Out_Valid <= S_P10_Valid; + S_P10_Ready <= S_Out_Ready; + S_Out_Data <= S_P10_Data; + when "01011" => + S_Out_Valid <= S_P11_Valid; + S_P11_Ready <= S_Out_Ready; + S_Out_Data <= S_P11_Data; + when "01100" => + S_Out_Valid <= S_P12_Valid; + S_P12_Ready <= S_Out_Ready; + S_Out_Data <= S_P12_Data; + when "01101" => + S_Out_Valid <= S_P13_Valid; + S_P13_Ready <= S_Out_Ready; + S_Out_Data <= S_P13_Data; + when "01110" => + S_Out_Valid <= S_P14_Valid; + S_P14_Ready <= S_Out_Ready; + S_Out_Data <= S_P14_Data; + when "01111" => + S_Out_Valid <= S_P15_Valid; + S_P15_Ready <= S_Out_Ready; + S_Out_Data <= S_P15_Data; + when "10000" => + S_Out_Valid <= S_P16_Valid; + S_P16_Ready <= S_Out_Ready; + S_Out_Data <= S_P16_Data; + when "10001" => + S_Out_Valid <= S_P17_Valid; + S_P17_Ready <= S_Out_Ready; + S_Out_Data <= S_P17_Data; + when "10010" => + S_Out_Valid <= S_P18_Valid; + S_P18_Ready <= S_Out_Ready; + S_Out_Data <= S_P18_Data; + when "10011" => + S_Out_Valid <= S_P19_Valid; + S_P19_Ready <= S_Out_Ready; + S_Out_Data <= S_P19_Data; + when "10100" => + S_Out_Valid <= S_P20_Valid; + S_P20_Ready <= S_Out_Ready; + S_Out_Data <= S_P20_Data; + when "10101" => + S_Out_Valid <= S_P21_Valid; + S_P21_Ready <= S_Out_Ready; + S_Out_Data <= S_P21_Data; + when "10110" => + S_Out_Valid <= S_P22_Valid; + S_P22_Ready <= S_Out_Ready; + S_Out_Data <= S_P22_Data; + when "10111" => + S_Out_Valid <= S_P23_Valid; + S_P23_Ready <= S_Out_Ready; + S_Out_Data <= S_P23_Data; + when "11000" => + S_Out_Valid <= S_P24_Valid; + S_P24_Ready <= S_Out_Ready; + S_Out_Data <= S_P24_Data; + when "11001" => + S_Out_Valid <= S_P25_Valid; + S_P25_Ready <= S_Out_Ready; + S_Out_Data <= S_P25_Data; + when "11010" => + S_Out_Valid <= S_P26_Valid; + S_P26_Ready <= S_Out_Ready; + S_Out_Data <= S_P26_Data; + when "11011" => + S_Out_Valid <= S_P27_Valid; + S_P27_Ready <= S_Out_Ready; + S_Out_Data <= S_P27_Data; + when "11100" => + S_Out_Valid <= S_P28_Valid; + S_P28_Ready <= S_Out_Ready; + S_Out_Data <= S_P28_Data; + when "11101" => + S_Out_Valid <= S_P29_Valid; + S_P29_Ready <= S_Out_Ready; + S_Out_Data <= S_P29_Data; + when "11110" => + S_Out_Valid <= S_P30_Valid; + S_P30_Ready <= S_Out_Ready; + S_Out_Data <= S_P30_Data; + when "11111" => + S_Out_Valid <= S_P31_Valid; + S_P31_Ready <= S_Out_Ready; + S_Out_Data <= S_P31_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 5, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/build/AXI_Handshaking_Scheduler_4.vhdl b/build/AXI_Handshaking_Scheduler_4.vhdl new file mode 100644 index 0000000..37389f9 --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_4.vhdl @@ -0,0 +1,309 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_4 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P2 @dir in P2 interface + I_P2_Valid : in std_logic := '0'; + O_P2_Ready : out std_logic := '0'; + I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P3 @dir in P3 interface + I_P3_Valid : in std_logic := '0'; + O_P3_Ready : out std_logic := '0'; + I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(1 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_4; + +architecture Rtl of AXI_Handshaking_Scheduler_4 is + signal R_SelectRotator : unsigned(1 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(1 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(3 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(1 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(1 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(1 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P2_InBufferEnable : std_logic := '0'; + signal S_P2_Ready : std_logic := '0'; + signal S_P2_Valid : std_logic := '0'; + signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P3_InBufferEnable : std_logic := '0'; + signal S_P3_Ready : std_logic := '0'; + signal S_P3_Valid : std_logic := '0'; + signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(1 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + I_P2_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P2_InBufferEnable, + I_Valid => I_P2_Valid, + O_Ready => O_P2_Ready, + O_Valid => S_P2_Valid, + I_Ready => S_P2_Ready + ); + + I_P2_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P2_InBufferEnable, + I_Data => I_P2_Data, + O_Data => S_P2_Data + ); + I_P3_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P3_InBufferEnable, + I_Valid => I_P3_Valid, + O_Ready => O_P3_Ready, + O_Valid => S_P3_Valid, + I_Ready => S_P3_Ready + ); + + I_P3_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P3_InBufferEnable, + I_Data => I_P3_Data, + O_Data => S_P3_Data + ); + + I_PriorityEncoder_4 : entity work.PriorityEncoder_4 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid) + begin + case R_SelectRotator is when "00" => + C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid; + when "01" => + C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P0_Valid; + when "10" => + C_Select <= S_P2_Valid & S_P3_Valid & S_P0_Valid & S_P1_Valid; + when "11" => + C_Select <= S_P3_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_P2_Ready <= '0'; + S_P3_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "00" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "01" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when "10" => + S_Out_Valid <= S_P2_Valid; + S_P2_Ready <= S_Out_Ready; + S_Out_Data <= S_P2_Data; + when "11" => + S_Out_Valid <= S_P3_Valid; + S_P3_Ready <= S_Out_Ready; + S_Out_Data <= S_P3_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 2, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/build/AXI_Handshaking_Scheduler_64.vhdl b/build/AXI_Handshaking_Scheduler_64.vhdl new file mode 100644 index 0000000..9fac3fe --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_64.vhdl @@ -0,0 +1,2889 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_64 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P2 @dir in P2 interface + I_P2_Valid : in std_logic := '0'; + O_P2_Ready : out std_logic := '0'; + I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P3 @dir in P3 interface + I_P3_Valid : in std_logic := '0'; + O_P3_Ready : out std_logic := '0'; + I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P4 @dir in P4 interface + I_P4_Valid : in std_logic := '0'; + O_P4_Ready : out std_logic := '0'; + I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P5 @dir in P5 interface + I_P5_Valid : in std_logic := '0'; + O_P5_Ready : out std_logic := '0'; + I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P6 @dir in P6 interface + I_P6_Valid : in std_logic := '0'; + O_P6_Ready : out std_logic := '0'; + I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P7 @dir in P7 interface + I_P7_Valid : in std_logic := '0'; + O_P7_Ready : out std_logic := '0'; + I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P8 @dir in P8 interface + I_P8_Valid : in std_logic := '0'; + O_P8_Ready : out std_logic := '0'; + I_P8_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P9 @dir in P9 interface + I_P9_Valid : in std_logic := '0'; + O_P9_Ready : out std_logic := '0'; + I_P9_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P10 @dir in P10 interface + I_P10_Valid : in std_logic := '0'; + O_P10_Ready : out std_logic := '0'; + I_P10_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P11 @dir in P11 interface + I_P11_Valid : in std_logic := '0'; + O_P11_Ready : out std_logic := '0'; + I_P11_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P12 @dir in P12 interface + I_P12_Valid : in std_logic := '0'; + O_P12_Ready : out std_logic := '0'; + I_P12_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P13 @dir in P13 interface + I_P13_Valid : in std_logic := '0'; + O_P13_Ready : out std_logic := '0'; + I_P13_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P14 @dir in P14 interface + I_P14_Valid : in std_logic := '0'; + O_P14_Ready : out std_logic := '0'; + I_P14_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P15 @dir in P15 interface + I_P15_Valid : in std_logic := '0'; + O_P15_Ready : out std_logic := '0'; + I_P15_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P16 @dir in P16 interface + I_P16_Valid : in std_logic := '0'; + O_P16_Ready : out std_logic := '0'; + I_P16_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P17 @dir in P17 interface + I_P17_Valid : in std_logic := '0'; + O_P17_Ready : out std_logic := '0'; + I_P17_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P18 @dir in P18 interface + I_P18_Valid : in std_logic := '0'; + O_P18_Ready : out std_logic := '0'; + I_P18_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P19 @dir in P19 interface + I_P19_Valid : in std_logic := '0'; + O_P19_Ready : out std_logic := '0'; + I_P19_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P20 @dir in P20 interface + I_P20_Valid : in std_logic := '0'; + O_P20_Ready : out std_logic := '0'; + I_P20_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P21 @dir in P21 interface + I_P21_Valid : in std_logic := '0'; + O_P21_Ready : out std_logic := '0'; + I_P21_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P22 @dir in P22 interface + I_P22_Valid : in std_logic := '0'; + O_P22_Ready : out std_logic := '0'; + I_P22_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P23 @dir in P23 interface + I_P23_Valid : in std_logic := '0'; + O_P23_Ready : out std_logic := '0'; + I_P23_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P24 @dir in P24 interface + I_P24_Valid : in std_logic := '0'; + O_P24_Ready : out std_logic := '0'; + I_P24_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P25 @dir in P25 interface + I_P25_Valid : in std_logic := '0'; + O_P25_Ready : out std_logic := '0'; + I_P25_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P26 @dir in P26 interface + I_P26_Valid : in std_logic := '0'; + O_P26_Ready : out std_logic := '0'; + I_P26_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P27 @dir in P27 interface + I_P27_Valid : in std_logic := '0'; + O_P27_Ready : out std_logic := '0'; + I_P27_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P28 @dir in P28 interface + I_P28_Valid : in std_logic := '0'; + O_P28_Ready : out std_logic := '0'; + I_P28_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P29 @dir in P29 interface + I_P29_Valid : in std_logic := '0'; + O_P29_Ready : out std_logic := '0'; + I_P29_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P30 @dir in P30 interface + I_P30_Valid : in std_logic := '0'; + O_P30_Ready : out std_logic := '0'; + I_P30_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P31 @dir in P31 interface + I_P31_Valid : in std_logic := '0'; + O_P31_Ready : out std_logic := '0'; + I_P31_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P32 @dir in P32 interface + I_P32_Valid : in std_logic := '0'; + O_P32_Ready : out std_logic := '0'; + I_P32_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P33 @dir in P33 interface + I_P33_Valid : in std_logic := '0'; + O_P33_Ready : out std_logic := '0'; + I_P33_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P34 @dir in P34 interface + I_P34_Valid : in std_logic := '0'; + O_P34_Ready : out std_logic := '0'; + I_P34_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P35 @dir in P35 interface + I_P35_Valid : in std_logic := '0'; + O_P35_Ready : out std_logic := '0'; + I_P35_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P36 @dir in P36 interface + I_P36_Valid : in std_logic := '0'; + O_P36_Ready : out std_logic := '0'; + I_P36_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P37 @dir in P37 interface + I_P37_Valid : in std_logic := '0'; + O_P37_Ready : out std_logic := '0'; + I_P37_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P38 @dir in P38 interface + I_P38_Valid : in std_logic := '0'; + O_P38_Ready : out std_logic := '0'; + I_P38_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P39 @dir in P39 interface + I_P39_Valid : in std_logic := '0'; + O_P39_Ready : out std_logic := '0'; + I_P39_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P40 @dir in P40 interface + I_P40_Valid : in std_logic := '0'; + O_P40_Ready : out std_logic := '0'; + I_P40_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P41 @dir in P41 interface + I_P41_Valid : in std_logic := '0'; + O_P41_Ready : out std_logic := '0'; + I_P41_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P42 @dir in P42 interface + I_P42_Valid : in std_logic := '0'; + O_P42_Ready : out std_logic := '0'; + I_P42_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P43 @dir in P43 interface + I_P43_Valid : in std_logic := '0'; + O_P43_Ready : out std_logic := '0'; + I_P43_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P44 @dir in P44 interface + I_P44_Valid : in std_logic := '0'; + O_P44_Ready : out std_logic := '0'; + I_P44_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P45 @dir in P45 interface + I_P45_Valid : in std_logic := '0'; + O_P45_Ready : out std_logic := '0'; + I_P45_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P46 @dir in P46 interface + I_P46_Valid : in std_logic := '0'; + O_P46_Ready : out std_logic := '0'; + I_P46_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P47 @dir in P47 interface + I_P47_Valid : in std_logic := '0'; + O_P47_Ready : out std_logic := '0'; + I_P47_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P48 @dir in P48 interface + I_P48_Valid : in std_logic := '0'; + O_P48_Ready : out std_logic := '0'; + I_P48_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P49 @dir in P49 interface + I_P49_Valid : in std_logic := '0'; + O_P49_Ready : out std_logic := '0'; + I_P49_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P50 @dir in P50 interface + I_P50_Valid : in std_logic := '0'; + O_P50_Ready : out std_logic := '0'; + I_P50_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P51 @dir in P51 interface + I_P51_Valid : in std_logic := '0'; + O_P51_Ready : out std_logic := '0'; + I_P51_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P52 @dir in P52 interface + I_P52_Valid : in std_logic := '0'; + O_P52_Ready : out std_logic := '0'; + I_P52_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P53 @dir in P53 interface + I_P53_Valid : in std_logic := '0'; + O_P53_Ready : out std_logic := '0'; + I_P53_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P54 @dir in P54 interface + I_P54_Valid : in std_logic := '0'; + O_P54_Ready : out std_logic := '0'; + I_P54_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P55 @dir in P55 interface + I_P55_Valid : in std_logic := '0'; + O_P55_Ready : out std_logic := '0'; + I_P55_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P56 @dir in P56 interface + I_P56_Valid : in std_logic := '0'; + O_P56_Ready : out std_logic := '0'; + I_P56_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P57 @dir in P57 interface + I_P57_Valid : in std_logic := '0'; + O_P57_Ready : out std_logic := '0'; + I_P57_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P58 @dir in P58 interface + I_P58_Valid : in std_logic := '0'; + O_P58_Ready : out std_logic := '0'; + I_P58_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P59 @dir in P59 interface + I_P59_Valid : in std_logic := '0'; + O_P59_Ready : out std_logic := '0'; + I_P59_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P60 @dir in P60 interface + I_P60_Valid : in std_logic := '0'; + O_P60_Ready : out std_logic := '0'; + I_P60_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P61 @dir in P61 interface + I_P61_Valid : in std_logic := '0'; + O_P61_Ready : out std_logic := '0'; + I_P61_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P62 @dir in P62 interface + I_P62_Valid : in std_logic := '0'; + O_P62_Ready : out std_logic := '0'; + I_P62_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P63 @dir in P63 interface + I_P63_Valid : in std_logic := '0'; + O_P63_Ready : out std_logic := '0'; + I_P63_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(5 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_64; + +architecture Rtl of AXI_Handshaking_Scheduler_64 is + signal R_SelectRotator : unsigned(5 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(5 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(63 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(5 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(5 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(5 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P2_InBufferEnable : std_logic := '0'; + signal S_P2_Ready : std_logic := '0'; + signal S_P2_Valid : std_logic := '0'; + signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P3_InBufferEnable : std_logic := '0'; + signal S_P3_Ready : std_logic := '0'; + signal S_P3_Valid : std_logic := '0'; + signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P4_InBufferEnable : std_logic := '0'; + signal S_P4_Ready : std_logic := '0'; + signal S_P4_Valid : std_logic := '0'; + signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P5_InBufferEnable : std_logic := '0'; + signal S_P5_Ready : std_logic := '0'; + signal S_P5_Valid : std_logic := '0'; + signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P6_InBufferEnable : std_logic := '0'; + signal S_P6_Ready : std_logic := '0'; + signal S_P6_Valid : std_logic := '0'; + signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P7_InBufferEnable : std_logic := '0'; + signal S_P7_Ready : std_logic := '0'; + signal S_P7_Valid : std_logic := '0'; + signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P8_InBufferEnable : std_logic := '0'; + signal S_P8_Ready : std_logic := '0'; + signal S_P8_Valid : std_logic := '0'; + signal S_P8_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P9_InBufferEnable : std_logic := '0'; + signal S_P9_Ready : std_logic := '0'; + signal S_P9_Valid : std_logic := '0'; + signal S_P9_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P10_InBufferEnable : std_logic := '0'; + signal S_P10_Ready : std_logic := '0'; + signal S_P10_Valid : std_logic := '0'; + signal S_P10_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P11_InBufferEnable : std_logic := '0'; + signal S_P11_Ready : std_logic := '0'; + signal S_P11_Valid : std_logic := '0'; + signal S_P11_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P12_InBufferEnable : std_logic := '0'; + signal S_P12_Ready : std_logic := '0'; + signal S_P12_Valid : std_logic := '0'; + signal S_P12_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P13_InBufferEnable : std_logic := '0'; + signal S_P13_Ready : std_logic := '0'; + signal S_P13_Valid : std_logic := '0'; + signal S_P13_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P14_InBufferEnable : std_logic := '0'; + signal S_P14_Ready : std_logic := '0'; + signal S_P14_Valid : std_logic := '0'; + signal S_P14_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P15_InBufferEnable : std_logic := '0'; + signal S_P15_Ready : std_logic := '0'; + signal S_P15_Valid : std_logic := '0'; + signal S_P15_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P16_InBufferEnable : std_logic := '0'; + signal S_P16_Ready : std_logic := '0'; + signal S_P16_Valid : std_logic := '0'; + signal S_P16_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P17_InBufferEnable : std_logic := '0'; + signal S_P17_Ready : std_logic := '0'; + signal S_P17_Valid : std_logic := '0'; + signal S_P17_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P18_InBufferEnable : std_logic := '0'; + signal S_P18_Ready : std_logic := '0'; + signal S_P18_Valid : std_logic := '0'; + signal S_P18_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P19_InBufferEnable : std_logic := '0'; + signal S_P19_Ready : std_logic := '0'; + signal S_P19_Valid : std_logic := '0'; + signal S_P19_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P20_InBufferEnable : std_logic := '0'; + signal S_P20_Ready : std_logic := '0'; + signal S_P20_Valid : std_logic := '0'; + signal S_P20_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P21_InBufferEnable : std_logic := '0'; + signal S_P21_Ready : std_logic := '0'; + signal S_P21_Valid : std_logic := '0'; + signal S_P21_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P22_InBufferEnable : std_logic := '0'; + signal S_P22_Ready : std_logic := '0'; + signal S_P22_Valid : std_logic := '0'; + signal S_P22_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P23_InBufferEnable : std_logic := '0'; + signal S_P23_Ready : std_logic := '0'; + signal S_P23_Valid : std_logic := '0'; + signal S_P23_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P24_InBufferEnable : std_logic := '0'; + signal S_P24_Ready : std_logic := '0'; + signal S_P24_Valid : std_logic := '0'; + signal S_P24_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P25_InBufferEnable : std_logic := '0'; + signal S_P25_Ready : std_logic := '0'; + signal S_P25_Valid : std_logic := '0'; + signal S_P25_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P26_InBufferEnable : std_logic := '0'; + signal S_P26_Ready : std_logic := '0'; + signal S_P26_Valid : std_logic := '0'; + signal S_P26_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P27_InBufferEnable : std_logic := '0'; + signal S_P27_Ready : std_logic := '0'; + signal S_P27_Valid : std_logic := '0'; + signal S_P27_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P28_InBufferEnable : std_logic := '0'; + signal S_P28_Ready : std_logic := '0'; + signal S_P28_Valid : std_logic := '0'; + signal S_P28_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P29_InBufferEnable : std_logic := '0'; + signal S_P29_Ready : std_logic := '0'; + signal S_P29_Valid : std_logic := '0'; + signal S_P29_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P30_InBufferEnable : std_logic := '0'; + signal S_P30_Ready : std_logic := '0'; + signal S_P30_Valid : std_logic := '0'; + signal S_P30_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P31_InBufferEnable : std_logic := '0'; + signal S_P31_Ready : std_logic := '0'; + signal S_P31_Valid : std_logic := '0'; + signal S_P31_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P32_InBufferEnable : std_logic := '0'; + signal S_P32_Ready : std_logic := '0'; + signal S_P32_Valid : std_logic := '0'; + signal S_P32_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P33_InBufferEnable : std_logic := '0'; + signal S_P33_Ready : std_logic := '0'; + signal S_P33_Valid : std_logic := '0'; + signal S_P33_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P34_InBufferEnable : std_logic := '0'; + signal S_P34_Ready : std_logic := '0'; + signal S_P34_Valid : std_logic := '0'; + signal S_P34_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P35_InBufferEnable : std_logic := '0'; + signal S_P35_Ready : std_logic := '0'; + signal S_P35_Valid : std_logic := '0'; + signal S_P35_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P36_InBufferEnable : std_logic := '0'; + signal S_P36_Ready : std_logic := '0'; + signal S_P36_Valid : std_logic := '0'; + signal S_P36_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P37_InBufferEnable : std_logic := '0'; + signal S_P37_Ready : std_logic := '0'; + signal S_P37_Valid : std_logic := '0'; + signal S_P37_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P38_InBufferEnable : std_logic := '0'; + signal S_P38_Ready : std_logic := '0'; + signal S_P38_Valid : std_logic := '0'; + signal S_P38_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P39_InBufferEnable : std_logic := '0'; + signal S_P39_Ready : std_logic := '0'; + signal S_P39_Valid : std_logic := '0'; + signal S_P39_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P40_InBufferEnable : std_logic := '0'; + signal S_P40_Ready : std_logic := '0'; + signal S_P40_Valid : std_logic := '0'; + signal S_P40_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P41_InBufferEnable : std_logic := '0'; + signal S_P41_Ready : std_logic := '0'; + signal S_P41_Valid : std_logic := '0'; + signal S_P41_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P42_InBufferEnable : std_logic := '0'; + signal S_P42_Ready : std_logic := '0'; + signal S_P42_Valid : std_logic := '0'; + signal S_P42_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P43_InBufferEnable : std_logic := '0'; + signal S_P43_Ready : std_logic := '0'; + signal S_P43_Valid : std_logic := '0'; + signal S_P43_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P44_InBufferEnable : std_logic := '0'; + signal S_P44_Ready : std_logic := '0'; + signal S_P44_Valid : std_logic := '0'; + signal S_P44_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P45_InBufferEnable : std_logic := '0'; + signal S_P45_Ready : std_logic := '0'; + signal S_P45_Valid : std_logic := '0'; + signal S_P45_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P46_InBufferEnable : std_logic := '0'; + signal S_P46_Ready : std_logic := '0'; + signal S_P46_Valid : std_logic := '0'; + signal S_P46_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P47_InBufferEnable : std_logic := '0'; + signal S_P47_Ready : std_logic := '0'; + signal S_P47_Valid : std_logic := '0'; + signal S_P47_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P48_InBufferEnable : std_logic := '0'; + signal S_P48_Ready : std_logic := '0'; + signal S_P48_Valid : std_logic := '0'; + signal S_P48_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P49_InBufferEnable : std_logic := '0'; + signal S_P49_Ready : std_logic := '0'; + signal S_P49_Valid : std_logic := '0'; + signal S_P49_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P50_InBufferEnable : std_logic := '0'; + signal S_P50_Ready : std_logic := '0'; + signal S_P50_Valid : std_logic := '0'; + signal S_P50_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P51_InBufferEnable : std_logic := '0'; + signal S_P51_Ready : std_logic := '0'; + signal S_P51_Valid : std_logic := '0'; + signal S_P51_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P52_InBufferEnable : std_logic := '0'; + signal S_P52_Ready : std_logic := '0'; + signal S_P52_Valid : std_logic := '0'; + signal S_P52_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P53_InBufferEnable : std_logic := '0'; + signal S_P53_Ready : std_logic := '0'; + signal S_P53_Valid : std_logic := '0'; + signal S_P53_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P54_InBufferEnable : std_logic := '0'; + signal S_P54_Ready : std_logic := '0'; + signal S_P54_Valid : std_logic := '0'; + signal S_P54_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P55_InBufferEnable : std_logic := '0'; + signal S_P55_Ready : std_logic := '0'; + signal S_P55_Valid : std_logic := '0'; + signal S_P55_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P56_InBufferEnable : std_logic := '0'; + signal S_P56_Ready : std_logic := '0'; + signal S_P56_Valid : std_logic := '0'; + signal S_P56_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P57_InBufferEnable : std_logic := '0'; + signal S_P57_Ready : std_logic := '0'; + signal S_P57_Valid : std_logic := '0'; + signal S_P57_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P58_InBufferEnable : std_logic := '0'; + signal S_P58_Ready : std_logic := '0'; + signal S_P58_Valid : std_logic := '0'; + signal S_P58_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P59_InBufferEnable : std_logic := '0'; + signal S_P59_Ready : std_logic := '0'; + signal S_P59_Valid : std_logic := '0'; + signal S_P59_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P60_InBufferEnable : std_logic := '0'; + signal S_P60_Ready : std_logic := '0'; + signal S_P60_Valid : std_logic := '0'; + signal S_P60_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P61_InBufferEnable : std_logic := '0'; + signal S_P61_Ready : std_logic := '0'; + signal S_P61_Valid : std_logic := '0'; + signal S_P61_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P62_InBufferEnable : std_logic := '0'; + signal S_P62_Ready : std_logic := '0'; + signal S_P62_Valid : std_logic := '0'; + signal S_P62_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P63_InBufferEnable : std_logic := '0'; + signal S_P63_Ready : std_logic := '0'; + signal S_P63_Valid : std_logic := '0'; + signal S_P63_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(5 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + I_P2_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P2_InBufferEnable, + I_Valid => I_P2_Valid, + O_Ready => O_P2_Ready, + O_Valid => S_P2_Valid, + I_Ready => S_P2_Ready + ); + + I_P2_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P2_InBufferEnable, + I_Data => I_P2_Data, + O_Data => S_P2_Data + ); + I_P3_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P3_InBufferEnable, + I_Valid => I_P3_Valid, + O_Ready => O_P3_Ready, + O_Valid => S_P3_Valid, + I_Ready => S_P3_Ready + ); + + I_P3_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P3_InBufferEnable, + I_Data => I_P3_Data, + O_Data => S_P3_Data + ); + I_P4_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P4_InBufferEnable, + I_Valid => I_P4_Valid, + O_Ready => O_P4_Ready, + O_Valid => S_P4_Valid, + I_Ready => S_P4_Ready + ); + + I_P4_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P4_InBufferEnable, + I_Data => I_P4_Data, + O_Data => S_P4_Data + ); + I_P5_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P5_InBufferEnable, + I_Valid => I_P5_Valid, + O_Ready => O_P5_Ready, + O_Valid => S_P5_Valid, + I_Ready => S_P5_Ready + ); + + I_P5_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P5_InBufferEnable, + I_Data => I_P5_Data, + O_Data => S_P5_Data + ); + I_P6_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P6_InBufferEnable, + I_Valid => I_P6_Valid, + O_Ready => O_P6_Ready, + O_Valid => S_P6_Valid, + I_Ready => S_P6_Ready + ); + + I_P6_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P6_InBufferEnable, + I_Data => I_P6_Data, + O_Data => S_P6_Data + ); + I_P7_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P7_InBufferEnable, + I_Valid => I_P7_Valid, + O_Ready => O_P7_Ready, + O_Valid => S_P7_Valid, + I_Ready => S_P7_Ready + ); + + I_P7_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P7_InBufferEnable, + I_Data => I_P7_Data, + O_Data => S_P7_Data + ); + I_P8_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P8_InBufferEnable, + I_Valid => I_P8_Valid, + O_Ready => O_P8_Ready, + O_Valid => S_P8_Valid, + I_Ready => S_P8_Ready + ); + + I_P8_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P8_InBufferEnable, + I_Data => I_P8_Data, + O_Data => S_P8_Data + ); + I_P9_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P9_InBufferEnable, + I_Valid => I_P9_Valid, + O_Ready => O_P9_Ready, + O_Valid => S_P9_Valid, + I_Ready => S_P9_Ready + ); + + I_P9_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P9_InBufferEnable, + I_Data => I_P9_Data, + O_Data => S_P9_Data + ); + I_P10_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P10_InBufferEnable, + I_Valid => I_P10_Valid, + O_Ready => O_P10_Ready, + O_Valid => S_P10_Valid, + I_Ready => S_P10_Ready + ); + + I_P10_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P10_InBufferEnable, + I_Data => I_P10_Data, + O_Data => S_P10_Data + ); + I_P11_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P11_InBufferEnable, + I_Valid => I_P11_Valid, + O_Ready => O_P11_Ready, + O_Valid => S_P11_Valid, + I_Ready => S_P11_Ready + ); + + I_P11_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P11_InBufferEnable, + I_Data => I_P11_Data, + O_Data => S_P11_Data + ); + I_P12_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P12_InBufferEnable, + I_Valid => I_P12_Valid, + O_Ready => O_P12_Ready, + O_Valid => S_P12_Valid, + I_Ready => S_P12_Ready + ); + + I_P12_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P12_InBufferEnable, + I_Data => I_P12_Data, + O_Data => S_P12_Data + ); + I_P13_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P13_InBufferEnable, + I_Valid => I_P13_Valid, + O_Ready => O_P13_Ready, + O_Valid => S_P13_Valid, + I_Ready => S_P13_Ready + ); + + I_P13_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P13_InBufferEnable, + I_Data => I_P13_Data, + O_Data => S_P13_Data + ); + I_P14_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P14_InBufferEnable, + I_Valid => I_P14_Valid, + O_Ready => O_P14_Ready, + O_Valid => S_P14_Valid, + I_Ready => S_P14_Ready + ); + + I_P14_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P14_InBufferEnable, + I_Data => I_P14_Data, + O_Data => S_P14_Data + ); + I_P15_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P15_InBufferEnable, + I_Valid => I_P15_Valid, + O_Ready => O_P15_Ready, + O_Valid => S_P15_Valid, + I_Ready => S_P15_Ready + ); + + I_P15_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P15_InBufferEnable, + I_Data => I_P15_Data, + O_Data => S_P15_Data + ); + I_P16_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P16_InBufferEnable, + I_Valid => I_P16_Valid, + O_Ready => O_P16_Ready, + O_Valid => S_P16_Valid, + I_Ready => S_P16_Ready + ); + + I_P16_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P16_InBufferEnable, + I_Data => I_P16_Data, + O_Data => S_P16_Data + ); + I_P17_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P17_InBufferEnable, + I_Valid => I_P17_Valid, + O_Ready => O_P17_Ready, + O_Valid => S_P17_Valid, + I_Ready => S_P17_Ready + ); + + I_P17_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P17_InBufferEnable, + I_Data => I_P17_Data, + O_Data => S_P17_Data + ); + I_P18_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P18_InBufferEnable, + I_Valid => I_P18_Valid, + O_Ready => O_P18_Ready, + O_Valid => S_P18_Valid, + I_Ready => S_P18_Ready + ); + + I_P18_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P18_InBufferEnable, + I_Data => I_P18_Data, + O_Data => S_P18_Data + ); + I_P19_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P19_InBufferEnable, + I_Valid => I_P19_Valid, + O_Ready => O_P19_Ready, + O_Valid => S_P19_Valid, + I_Ready => S_P19_Ready + ); + + I_P19_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P19_InBufferEnable, + I_Data => I_P19_Data, + O_Data => S_P19_Data + ); + I_P20_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P20_InBufferEnable, + I_Valid => I_P20_Valid, + O_Ready => O_P20_Ready, + O_Valid => S_P20_Valid, + I_Ready => S_P20_Ready + ); + + I_P20_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P20_InBufferEnable, + I_Data => I_P20_Data, + O_Data => S_P20_Data + ); + I_P21_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P21_InBufferEnable, + I_Valid => I_P21_Valid, + O_Ready => O_P21_Ready, + O_Valid => S_P21_Valid, + I_Ready => S_P21_Ready + ); + + I_P21_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P21_InBufferEnable, + I_Data => I_P21_Data, + O_Data => S_P21_Data + ); + I_P22_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P22_InBufferEnable, + I_Valid => I_P22_Valid, + O_Ready => O_P22_Ready, + O_Valid => S_P22_Valid, + I_Ready => S_P22_Ready + ); + + I_P22_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P22_InBufferEnable, + I_Data => I_P22_Data, + O_Data => S_P22_Data + ); + I_P23_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P23_InBufferEnable, + I_Valid => I_P23_Valid, + O_Ready => O_P23_Ready, + O_Valid => S_P23_Valid, + I_Ready => S_P23_Ready + ); + + I_P23_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P23_InBufferEnable, + I_Data => I_P23_Data, + O_Data => S_P23_Data + ); + I_P24_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P24_InBufferEnable, + I_Valid => I_P24_Valid, + O_Ready => O_P24_Ready, + O_Valid => S_P24_Valid, + I_Ready => S_P24_Ready + ); + + I_P24_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P24_InBufferEnable, + I_Data => I_P24_Data, + O_Data => S_P24_Data + ); + I_P25_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P25_InBufferEnable, + I_Valid => I_P25_Valid, + O_Ready => O_P25_Ready, + O_Valid => S_P25_Valid, + I_Ready => S_P25_Ready + ); + + I_P25_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P25_InBufferEnable, + I_Data => I_P25_Data, + O_Data => S_P25_Data + ); + I_P26_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P26_InBufferEnable, + I_Valid => I_P26_Valid, + O_Ready => O_P26_Ready, + O_Valid => S_P26_Valid, + I_Ready => S_P26_Ready + ); + + I_P26_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P26_InBufferEnable, + I_Data => I_P26_Data, + O_Data => S_P26_Data + ); + I_P27_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P27_InBufferEnable, + I_Valid => I_P27_Valid, + O_Ready => O_P27_Ready, + O_Valid => S_P27_Valid, + I_Ready => S_P27_Ready + ); + + I_P27_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P27_InBufferEnable, + I_Data => I_P27_Data, + O_Data => S_P27_Data + ); + I_P28_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P28_InBufferEnable, + I_Valid => I_P28_Valid, + O_Ready => O_P28_Ready, + O_Valid => S_P28_Valid, + I_Ready => S_P28_Ready + ); + + I_P28_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P28_InBufferEnable, + I_Data => I_P28_Data, + O_Data => S_P28_Data + ); + I_P29_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P29_InBufferEnable, + I_Valid => I_P29_Valid, + O_Ready => O_P29_Ready, + O_Valid => S_P29_Valid, + I_Ready => S_P29_Ready + ); + + I_P29_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P29_InBufferEnable, + I_Data => I_P29_Data, + O_Data => S_P29_Data + ); + I_P30_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P30_InBufferEnable, + I_Valid => I_P30_Valid, + O_Ready => O_P30_Ready, + O_Valid => S_P30_Valid, + I_Ready => S_P30_Ready + ); + + I_P30_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P30_InBufferEnable, + I_Data => I_P30_Data, + O_Data => S_P30_Data + ); + I_P31_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P31_InBufferEnable, + I_Valid => I_P31_Valid, + O_Ready => O_P31_Ready, + O_Valid => S_P31_Valid, + I_Ready => S_P31_Ready + ); + + I_P31_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P31_InBufferEnable, + I_Data => I_P31_Data, + O_Data => S_P31_Data + ); + I_P32_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P32_InBufferEnable, + I_Valid => I_P32_Valid, + O_Ready => O_P32_Ready, + O_Valid => S_P32_Valid, + I_Ready => S_P32_Ready + ); + + I_P32_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P32_InBufferEnable, + I_Data => I_P32_Data, + O_Data => S_P32_Data + ); + I_P33_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P33_InBufferEnable, + I_Valid => I_P33_Valid, + O_Ready => O_P33_Ready, + O_Valid => S_P33_Valid, + I_Ready => S_P33_Ready + ); + + I_P33_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P33_InBufferEnable, + I_Data => I_P33_Data, + O_Data => S_P33_Data + ); + I_P34_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P34_InBufferEnable, + I_Valid => I_P34_Valid, + O_Ready => O_P34_Ready, + O_Valid => S_P34_Valid, + I_Ready => S_P34_Ready + ); + + I_P34_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P34_InBufferEnable, + I_Data => I_P34_Data, + O_Data => S_P34_Data + ); + I_P35_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P35_InBufferEnable, + I_Valid => I_P35_Valid, + O_Ready => O_P35_Ready, + O_Valid => S_P35_Valid, + I_Ready => S_P35_Ready + ); + + I_P35_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P35_InBufferEnable, + I_Data => I_P35_Data, + O_Data => S_P35_Data + ); + I_P36_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P36_InBufferEnable, + I_Valid => I_P36_Valid, + O_Ready => O_P36_Ready, + O_Valid => S_P36_Valid, + I_Ready => S_P36_Ready + ); + + I_P36_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P36_InBufferEnable, + I_Data => I_P36_Data, + O_Data => S_P36_Data + ); + I_P37_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P37_InBufferEnable, + I_Valid => I_P37_Valid, + O_Ready => O_P37_Ready, + O_Valid => S_P37_Valid, + I_Ready => S_P37_Ready + ); + + I_P37_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P37_InBufferEnable, + I_Data => I_P37_Data, + O_Data => S_P37_Data + ); + I_P38_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P38_InBufferEnable, + I_Valid => I_P38_Valid, + O_Ready => O_P38_Ready, + O_Valid => S_P38_Valid, + I_Ready => S_P38_Ready + ); + + I_P38_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P38_InBufferEnable, + I_Data => I_P38_Data, + O_Data => S_P38_Data + ); + I_P39_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P39_InBufferEnable, + I_Valid => I_P39_Valid, + O_Ready => O_P39_Ready, + O_Valid => S_P39_Valid, + I_Ready => S_P39_Ready + ); + + I_P39_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P39_InBufferEnable, + I_Data => I_P39_Data, + O_Data => S_P39_Data + ); + I_P40_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P40_InBufferEnable, + I_Valid => I_P40_Valid, + O_Ready => O_P40_Ready, + O_Valid => S_P40_Valid, + I_Ready => S_P40_Ready + ); + + I_P40_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P40_InBufferEnable, + I_Data => I_P40_Data, + O_Data => S_P40_Data + ); + I_P41_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P41_InBufferEnable, + I_Valid => I_P41_Valid, + O_Ready => O_P41_Ready, + O_Valid => S_P41_Valid, + I_Ready => S_P41_Ready + ); + + I_P41_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P41_InBufferEnable, + I_Data => I_P41_Data, + O_Data => S_P41_Data + ); + I_P42_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P42_InBufferEnable, + I_Valid => I_P42_Valid, + O_Ready => O_P42_Ready, + O_Valid => S_P42_Valid, + I_Ready => S_P42_Ready + ); + + I_P42_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P42_InBufferEnable, + I_Data => I_P42_Data, + O_Data => S_P42_Data + ); + I_P43_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P43_InBufferEnable, + I_Valid => I_P43_Valid, + O_Ready => O_P43_Ready, + O_Valid => S_P43_Valid, + I_Ready => S_P43_Ready + ); + + I_P43_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P43_InBufferEnable, + I_Data => I_P43_Data, + O_Data => S_P43_Data + ); + I_P44_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P44_InBufferEnable, + I_Valid => I_P44_Valid, + O_Ready => O_P44_Ready, + O_Valid => S_P44_Valid, + I_Ready => S_P44_Ready + ); + + I_P44_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P44_InBufferEnable, + I_Data => I_P44_Data, + O_Data => S_P44_Data + ); + I_P45_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P45_InBufferEnable, + I_Valid => I_P45_Valid, + O_Ready => O_P45_Ready, + O_Valid => S_P45_Valid, + I_Ready => S_P45_Ready + ); + + I_P45_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P45_InBufferEnable, + I_Data => I_P45_Data, + O_Data => S_P45_Data + ); + I_P46_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P46_InBufferEnable, + I_Valid => I_P46_Valid, + O_Ready => O_P46_Ready, + O_Valid => S_P46_Valid, + I_Ready => S_P46_Ready + ); + + I_P46_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P46_InBufferEnable, + I_Data => I_P46_Data, + O_Data => S_P46_Data + ); + I_P47_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P47_InBufferEnable, + I_Valid => I_P47_Valid, + O_Ready => O_P47_Ready, + O_Valid => S_P47_Valid, + I_Ready => S_P47_Ready + ); + + I_P47_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P47_InBufferEnable, + I_Data => I_P47_Data, + O_Data => S_P47_Data + ); + I_P48_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P48_InBufferEnable, + I_Valid => I_P48_Valid, + O_Ready => O_P48_Ready, + O_Valid => S_P48_Valid, + I_Ready => S_P48_Ready + ); + + I_P48_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P48_InBufferEnable, + I_Data => I_P48_Data, + O_Data => S_P48_Data + ); + I_P49_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P49_InBufferEnable, + I_Valid => I_P49_Valid, + O_Ready => O_P49_Ready, + O_Valid => S_P49_Valid, + I_Ready => S_P49_Ready + ); + + I_P49_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P49_InBufferEnable, + I_Data => I_P49_Data, + O_Data => S_P49_Data + ); + I_P50_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P50_InBufferEnable, + I_Valid => I_P50_Valid, + O_Ready => O_P50_Ready, + O_Valid => S_P50_Valid, + I_Ready => S_P50_Ready + ); + + I_P50_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P50_InBufferEnable, + I_Data => I_P50_Data, + O_Data => S_P50_Data + ); + I_P51_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P51_InBufferEnable, + I_Valid => I_P51_Valid, + O_Ready => O_P51_Ready, + O_Valid => S_P51_Valid, + I_Ready => S_P51_Ready + ); + + I_P51_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P51_InBufferEnable, + I_Data => I_P51_Data, + O_Data => S_P51_Data + ); + I_P52_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P52_InBufferEnable, + I_Valid => I_P52_Valid, + O_Ready => O_P52_Ready, + O_Valid => S_P52_Valid, + I_Ready => S_P52_Ready + ); + + I_P52_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P52_InBufferEnable, + I_Data => I_P52_Data, + O_Data => S_P52_Data + ); + I_P53_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P53_InBufferEnable, + I_Valid => I_P53_Valid, + O_Ready => O_P53_Ready, + O_Valid => S_P53_Valid, + I_Ready => S_P53_Ready + ); + + I_P53_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P53_InBufferEnable, + I_Data => I_P53_Data, + O_Data => S_P53_Data + ); + I_P54_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P54_InBufferEnable, + I_Valid => I_P54_Valid, + O_Ready => O_P54_Ready, + O_Valid => S_P54_Valid, + I_Ready => S_P54_Ready + ); + + I_P54_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P54_InBufferEnable, + I_Data => I_P54_Data, + O_Data => S_P54_Data + ); + I_P55_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P55_InBufferEnable, + I_Valid => I_P55_Valid, + O_Ready => O_P55_Ready, + O_Valid => S_P55_Valid, + I_Ready => S_P55_Ready + ); + + I_P55_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P55_InBufferEnable, + I_Data => I_P55_Data, + O_Data => S_P55_Data + ); + I_P56_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P56_InBufferEnable, + I_Valid => I_P56_Valid, + O_Ready => O_P56_Ready, + O_Valid => S_P56_Valid, + I_Ready => S_P56_Ready + ); + + I_P56_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P56_InBufferEnable, + I_Data => I_P56_Data, + O_Data => S_P56_Data + ); + I_P57_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P57_InBufferEnable, + I_Valid => I_P57_Valid, + O_Ready => O_P57_Ready, + O_Valid => S_P57_Valid, + I_Ready => S_P57_Ready + ); + + I_P57_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P57_InBufferEnable, + I_Data => I_P57_Data, + O_Data => S_P57_Data + ); + I_P58_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P58_InBufferEnable, + I_Valid => I_P58_Valid, + O_Ready => O_P58_Ready, + O_Valid => S_P58_Valid, + I_Ready => S_P58_Ready + ); + + I_P58_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P58_InBufferEnable, + I_Data => I_P58_Data, + O_Data => S_P58_Data + ); + I_P59_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P59_InBufferEnable, + I_Valid => I_P59_Valid, + O_Ready => O_P59_Ready, + O_Valid => S_P59_Valid, + I_Ready => S_P59_Ready + ); + + I_P59_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P59_InBufferEnable, + I_Data => I_P59_Data, + O_Data => S_P59_Data + ); + I_P60_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P60_InBufferEnable, + I_Valid => I_P60_Valid, + O_Ready => O_P60_Ready, + O_Valid => S_P60_Valid, + I_Ready => S_P60_Ready + ); + + I_P60_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P60_InBufferEnable, + I_Data => I_P60_Data, + O_Data => S_P60_Data + ); + I_P61_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P61_InBufferEnable, + I_Valid => I_P61_Valid, + O_Ready => O_P61_Ready, + O_Valid => S_P61_Valid, + I_Ready => S_P61_Ready + ); + + I_P61_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P61_InBufferEnable, + I_Data => I_P61_Data, + O_Data => S_P61_Data + ); + I_P62_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P62_InBufferEnable, + I_Valid => I_P62_Valid, + O_Ready => O_P62_Ready, + O_Valid => S_P62_Valid, + I_Ready => S_P62_Ready + ); + + I_P62_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P62_InBufferEnable, + I_Data => I_P62_Data, + O_Data => S_P62_Data + ); + I_P63_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P63_InBufferEnable, + I_Valid => I_P63_Valid, + O_Ready => O_P63_Ready, + O_Valid => S_P63_Valid, + I_Ready => S_P63_Ready + ); + + I_P63_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P63_InBufferEnable, + I_Data => I_P63_Data, + O_Data => S_P63_Data + ); + + I_PriorityEncoder_64 : entity work.PriorityEncoder_64 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_P16_Valid, S_P17_Valid, S_P18_Valid, S_P19_Valid, S_P20_Valid, S_P21_Valid, S_P22_Valid, S_P23_Valid, S_P24_Valid, S_P25_Valid, S_P26_Valid, S_P27_Valid, S_P28_Valid, S_P29_Valid, S_P30_Valid, S_P31_Valid, S_P32_Valid, S_P33_Valid, S_P34_Valid, S_P35_Valid, S_P36_Valid, S_P37_Valid, S_P38_Valid, S_P39_Valid, S_P40_Valid, S_P41_Valid, S_P42_Valid, S_P43_Valid, S_P44_Valid, S_P45_Valid, S_P46_Valid, S_P47_Valid, S_P48_Valid, S_P49_Valid, S_P50_Valid, S_P51_Valid, S_P52_Valid, S_P53_Valid, S_P54_Valid, S_P55_Valid, S_P56_Valid, S_P57_Valid, S_P58_Valid, S_P59_Valid, S_P60_Valid, S_P61_Valid, S_P62_Valid, S_P63_Valid) + begin + case R_SelectRotator is when "000000" => + C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid; + when "000001" => + C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid; + when "000010" => + C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid; + when "000011" => + C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid; + when "000100" => + C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid; + when "000101" => + C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid; + when "000110" => + C_Select <= S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid; + when "000111" => + C_Select <= S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid; + when "001000" => + C_Select <= S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid; + when "001001" => + C_Select <= S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid; + when "001010" => + C_Select <= S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid; + when "001011" => + C_Select <= S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid; + when "001100" => + C_Select <= S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid; + when "001101" => + C_Select <= S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid; + when "001110" => + C_Select <= S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid; + when "001111" => + C_Select <= S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid; + when "010000" => + C_Select <= S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid; + when "010001" => + C_Select <= S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid; + when "010010" => + C_Select <= S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid; + when "010011" => + C_Select <= S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid; + when "010100" => + C_Select <= S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid; + when "010101" => + C_Select <= S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid; + when "010110" => + C_Select <= S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid; + when "010111" => + C_Select <= S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid; + when "011000" => + C_Select <= S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid; + when "011001" => + C_Select <= S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid; + when "011010" => + C_Select <= S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid; + when "011011" => + C_Select <= S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid; + when "011100" => + C_Select <= S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid; + when "011101" => + C_Select <= S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid; + when "011110" => + C_Select <= S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid; + when "011111" => + C_Select <= S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid; + when "100000" => + C_Select <= S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid; + when "100001" => + C_Select <= S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid; + when "100010" => + C_Select <= S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid; + when "100011" => + C_Select <= S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid; + when "100100" => + C_Select <= S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid; + when "100101" => + C_Select <= S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid; + when "100110" => + C_Select <= S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid; + when "100111" => + C_Select <= S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid; + when "101000" => + C_Select <= S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid; + when "101001" => + C_Select <= S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid; + when "101010" => + C_Select <= S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid; + when "101011" => + C_Select <= S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid; + when "101100" => + C_Select <= S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid; + when "101101" => + C_Select <= S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid; + when "101110" => + C_Select <= S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid; + when "101111" => + C_Select <= S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid; + when "110000" => + C_Select <= S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid; + when "110001" => + C_Select <= S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid; + when "110010" => + C_Select <= S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid; + when "110011" => + C_Select <= S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid; + when "110100" => + C_Select <= S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid; + when "110101" => + C_Select <= S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid; + when "110110" => + C_Select <= S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid; + when "110111" => + C_Select <= S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid; + when "111000" => + C_Select <= S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid; + when "111001" => + C_Select <= S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid; + when "111010" => + C_Select <= S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid; + when "111011" => + C_Select <= S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid; + when "111100" => + C_Select <= S_P60_Valid & S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid; + when "111101" => + C_Select <= S_P61_Valid & S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid; + when "111110" => + C_Select <= S_P62_Valid & S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid; + when "111111" => + C_Select <= S_P63_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P16_Valid & S_P17_Valid & S_P18_Valid & S_P19_Valid & S_P20_Valid & S_P21_Valid & S_P22_Valid & S_P23_Valid & S_P24_Valid & S_P25_Valid & S_P26_Valid & S_P27_Valid & S_P28_Valid & S_P29_Valid & S_P30_Valid & S_P31_Valid & S_P32_Valid & S_P33_Valid & S_P34_Valid & S_P35_Valid & S_P36_Valid & S_P37_Valid & S_P38_Valid & S_P39_Valid & S_P40_Valid & S_P41_Valid & S_P42_Valid & S_P43_Valid & S_P44_Valid & S_P45_Valid & S_P46_Valid & S_P47_Valid & S_P48_Valid & S_P49_Valid & S_P50_Valid & S_P51_Valid & S_P52_Valid & S_P53_Valid & S_P54_Valid & S_P55_Valid & S_P56_Valid & S_P57_Valid & S_P58_Valid & S_P59_Valid & S_P60_Valid & S_P61_Valid & S_P62_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P8_Data, S_P9_Data, S_P10_Data, S_P11_Data, S_P12_Data, S_P13_Data, S_P14_Data, S_P15_Data, S_P16_Data, S_P17_Data, S_P18_Data, S_P19_Data, S_P20_Data, S_P21_Data, S_P22_Data, S_P23_Data, S_P24_Data, S_P25_Data, S_P26_Data, S_P27_Data, S_P28_Data, S_P29_Data, S_P30_Data, S_P31_Data, S_P32_Data, S_P33_Data, S_P34_Data, S_P35_Data, S_P36_Data, S_P37_Data, S_P38_Data, S_P39_Data, S_P40_Data, S_P41_Data, S_P42_Data, S_P43_Data, S_P44_Data, S_P45_Data, S_P46_Data, S_P47_Data, S_P48_Data, S_P49_Data, S_P50_Data, S_P51_Data, S_P52_Data, S_P53_Data, S_P54_Data, S_P55_Data, S_P56_Data, S_P57_Data, S_P58_Data, S_P59_Data, S_P60_Data, S_P61_Data, S_P62_Data, S_P63_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_P16_Valid, S_P17_Valid, S_P18_Valid, S_P19_Valid, S_P20_Valid, S_P21_Valid, S_P22_Valid, S_P23_Valid, S_P24_Valid, S_P25_Valid, S_P26_Valid, S_P27_Valid, S_P28_Valid, S_P29_Valid, S_P30_Valid, S_P31_Valid, S_P32_Valid, S_P33_Valid, S_P34_Valid, S_P35_Valid, S_P36_Valid, S_P37_Valid, S_P38_Valid, S_P39_Valid, S_P40_Valid, S_P41_Valid, S_P42_Valid, S_P43_Valid, S_P44_Valid, S_P45_Valid, S_P46_Valid, S_P47_Valid, S_P48_Valid, S_P49_Valid, S_P50_Valid, S_P51_Valid, S_P52_Valid, S_P53_Valid, S_P54_Valid, S_P55_Valid, S_P56_Valid, S_P57_Valid, S_P58_Valid, S_P59_Valid, S_P60_Valid, S_P61_Valid, S_P62_Valid, S_P63_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_P2_Ready <= '0'; + S_P3_Ready <= '0'; + S_P4_Ready <= '0'; + S_P5_Ready <= '0'; + S_P6_Ready <= '0'; + S_P7_Ready <= '0'; + S_P8_Ready <= '0'; + S_P9_Ready <= '0'; + S_P10_Ready <= '0'; + S_P11_Ready <= '0'; + S_P12_Ready <= '0'; + S_P13_Ready <= '0'; + S_P14_Ready <= '0'; + S_P15_Ready <= '0'; + S_P16_Ready <= '0'; + S_P17_Ready <= '0'; + S_P18_Ready <= '0'; + S_P19_Ready <= '0'; + S_P20_Ready <= '0'; + S_P21_Ready <= '0'; + S_P22_Ready <= '0'; + S_P23_Ready <= '0'; + S_P24_Ready <= '0'; + S_P25_Ready <= '0'; + S_P26_Ready <= '0'; + S_P27_Ready <= '0'; + S_P28_Ready <= '0'; + S_P29_Ready <= '0'; + S_P30_Ready <= '0'; + S_P31_Ready <= '0'; + S_P32_Ready <= '0'; + S_P33_Ready <= '0'; + S_P34_Ready <= '0'; + S_P35_Ready <= '0'; + S_P36_Ready <= '0'; + S_P37_Ready <= '0'; + S_P38_Ready <= '0'; + S_P39_Ready <= '0'; + S_P40_Ready <= '0'; + S_P41_Ready <= '0'; + S_P42_Ready <= '0'; + S_P43_Ready <= '0'; + S_P44_Ready <= '0'; + S_P45_Ready <= '0'; + S_P46_Ready <= '0'; + S_P47_Ready <= '0'; + S_P48_Ready <= '0'; + S_P49_Ready <= '0'; + S_P50_Ready <= '0'; + S_P51_Ready <= '0'; + S_P52_Ready <= '0'; + S_P53_Ready <= '0'; + S_P54_Ready <= '0'; + S_P55_Ready <= '0'; + S_P56_Ready <= '0'; + S_P57_Ready <= '0'; + S_P58_Ready <= '0'; + S_P59_Ready <= '0'; + S_P60_Ready <= '0'; + S_P61_Ready <= '0'; + S_P62_Ready <= '0'; + S_P63_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "000000" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "000001" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when "000010" => + S_Out_Valid <= S_P2_Valid; + S_P2_Ready <= S_Out_Ready; + S_Out_Data <= S_P2_Data; + when "000011" => + S_Out_Valid <= S_P3_Valid; + S_P3_Ready <= S_Out_Ready; + S_Out_Data <= S_P3_Data; + when "000100" => + S_Out_Valid <= S_P4_Valid; + S_P4_Ready <= S_Out_Ready; + S_Out_Data <= S_P4_Data; + when "000101" => + S_Out_Valid <= S_P5_Valid; + S_P5_Ready <= S_Out_Ready; + S_Out_Data <= S_P5_Data; + when "000110" => + S_Out_Valid <= S_P6_Valid; + S_P6_Ready <= S_Out_Ready; + S_Out_Data <= S_P6_Data; + when "000111" => + S_Out_Valid <= S_P7_Valid; + S_P7_Ready <= S_Out_Ready; + S_Out_Data <= S_P7_Data; + when "001000" => + S_Out_Valid <= S_P8_Valid; + S_P8_Ready <= S_Out_Ready; + S_Out_Data <= S_P8_Data; + when "001001" => + S_Out_Valid <= S_P9_Valid; + S_P9_Ready <= S_Out_Ready; + S_Out_Data <= S_P9_Data; + when "001010" => + S_Out_Valid <= S_P10_Valid; + S_P10_Ready <= S_Out_Ready; + S_Out_Data <= S_P10_Data; + when "001011" => + S_Out_Valid <= S_P11_Valid; + S_P11_Ready <= S_Out_Ready; + S_Out_Data <= S_P11_Data; + when "001100" => + S_Out_Valid <= S_P12_Valid; + S_P12_Ready <= S_Out_Ready; + S_Out_Data <= S_P12_Data; + when "001101" => + S_Out_Valid <= S_P13_Valid; + S_P13_Ready <= S_Out_Ready; + S_Out_Data <= S_P13_Data; + when "001110" => + S_Out_Valid <= S_P14_Valid; + S_P14_Ready <= S_Out_Ready; + S_Out_Data <= S_P14_Data; + when "001111" => + S_Out_Valid <= S_P15_Valid; + S_P15_Ready <= S_Out_Ready; + S_Out_Data <= S_P15_Data; + when "010000" => + S_Out_Valid <= S_P16_Valid; + S_P16_Ready <= S_Out_Ready; + S_Out_Data <= S_P16_Data; + when "010001" => + S_Out_Valid <= S_P17_Valid; + S_P17_Ready <= S_Out_Ready; + S_Out_Data <= S_P17_Data; + when "010010" => + S_Out_Valid <= S_P18_Valid; + S_P18_Ready <= S_Out_Ready; + S_Out_Data <= S_P18_Data; + when "010011" => + S_Out_Valid <= S_P19_Valid; + S_P19_Ready <= S_Out_Ready; + S_Out_Data <= S_P19_Data; + when "010100" => + S_Out_Valid <= S_P20_Valid; + S_P20_Ready <= S_Out_Ready; + S_Out_Data <= S_P20_Data; + when "010101" => + S_Out_Valid <= S_P21_Valid; + S_P21_Ready <= S_Out_Ready; + S_Out_Data <= S_P21_Data; + when "010110" => + S_Out_Valid <= S_P22_Valid; + S_P22_Ready <= S_Out_Ready; + S_Out_Data <= S_P22_Data; + when "010111" => + S_Out_Valid <= S_P23_Valid; + S_P23_Ready <= S_Out_Ready; + S_Out_Data <= S_P23_Data; + when "011000" => + S_Out_Valid <= S_P24_Valid; + S_P24_Ready <= S_Out_Ready; + S_Out_Data <= S_P24_Data; + when "011001" => + S_Out_Valid <= S_P25_Valid; + S_P25_Ready <= S_Out_Ready; + S_Out_Data <= S_P25_Data; + when "011010" => + S_Out_Valid <= S_P26_Valid; + S_P26_Ready <= S_Out_Ready; + S_Out_Data <= S_P26_Data; + when "011011" => + S_Out_Valid <= S_P27_Valid; + S_P27_Ready <= S_Out_Ready; + S_Out_Data <= S_P27_Data; + when "011100" => + S_Out_Valid <= S_P28_Valid; + S_P28_Ready <= S_Out_Ready; + S_Out_Data <= S_P28_Data; + when "011101" => + S_Out_Valid <= S_P29_Valid; + S_P29_Ready <= S_Out_Ready; + S_Out_Data <= S_P29_Data; + when "011110" => + S_Out_Valid <= S_P30_Valid; + S_P30_Ready <= S_Out_Ready; + S_Out_Data <= S_P30_Data; + when "011111" => + S_Out_Valid <= S_P31_Valid; + S_P31_Ready <= S_Out_Ready; + S_Out_Data <= S_P31_Data; + when "100000" => + S_Out_Valid <= S_P32_Valid; + S_P32_Ready <= S_Out_Ready; + S_Out_Data <= S_P32_Data; + when "100001" => + S_Out_Valid <= S_P33_Valid; + S_P33_Ready <= S_Out_Ready; + S_Out_Data <= S_P33_Data; + when "100010" => + S_Out_Valid <= S_P34_Valid; + S_P34_Ready <= S_Out_Ready; + S_Out_Data <= S_P34_Data; + when "100011" => + S_Out_Valid <= S_P35_Valid; + S_P35_Ready <= S_Out_Ready; + S_Out_Data <= S_P35_Data; + when "100100" => + S_Out_Valid <= S_P36_Valid; + S_P36_Ready <= S_Out_Ready; + S_Out_Data <= S_P36_Data; + when "100101" => + S_Out_Valid <= S_P37_Valid; + S_P37_Ready <= S_Out_Ready; + S_Out_Data <= S_P37_Data; + when "100110" => + S_Out_Valid <= S_P38_Valid; + S_P38_Ready <= S_Out_Ready; + S_Out_Data <= S_P38_Data; + when "100111" => + S_Out_Valid <= S_P39_Valid; + S_P39_Ready <= S_Out_Ready; + S_Out_Data <= S_P39_Data; + when "101000" => + S_Out_Valid <= S_P40_Valid; + S_P40_Ready <= S_Out_Ready; + S_Out_Data <= S_P40_Data; + when "101001" => + S_Out_Valid <= S_P41_Valid; + S_P41_Ready <= S_Out_Ready; + S_Out_Data <= S_P41_Data; + when "101010" => + S_Out_Valid <= S_P42_Valid; + S_P42_Ready <= S_Out_Ready; + S_Out_Data <= S_P42_Data; + when "101011" => + S_Out_Valid <= S_P43_Valid; + S_P43_Ready <= S_Out_Ready; + S_Out_Data <= S_P43_Data; + when "101100" => + S_Out_Valid <= S_P44_Valid; + S_P44_Ready <= S_Out_Ready; + S_Out_Data <= S_P44_Data; + when "101101" => + S_Out_Valid <= S_P45_Valid; + S_P45_Ready <= S_Out_Ready; + S_Out_Data <= S_P45_Data; + when "101110" => + S_Out_Valid <= S_P46_Valid; + S_P46_Ready <= S_Out_Ready; + S_Out_Data <= S_P46_Data; + when "101111" => + S_Out_Valid <= S_P47_Valid; + S_P47_Ready <= S_Out_Ready; + S_Out_Data <= S_P47_Data; + when "110000" => + S_Out_Valid <= S_P48_Valid; + S_P48_Ready <= S_Out_Ready; + S_Out_Data <= S_P48_Data; + when "110001" => + S_Out_Valid <= S_P49_Valid; + S_P49_Ready <= S_Out_Ready; + S_Out_Data <= S_P49_Data; + when "110010" => + S_Out_Valid <= S_P50_Valid; + S_P50_Ready <= S_Out_Ready; + S_Out_Data <= S_P50_Data; + when "110011" => + S_Out_Valid <= S_P51_Valid; + S_P51_Ready <= S_Out_Ready; + S_Out_Data <= S_P51_Data; + when "110100" => + S_Out_Valid <= S_P52_Valid; + S_P52_Ready <= S_Out_Ready; + S_Out_Data <= S_P52_Data; + when "110101" => + S_Out_Valid <= S_P53_Valid; + S_P53_Ready <= S_Out_Ready; + S_Out_Data <= S_P53_Data; + when "110110" => + S_Out_Valid <= S_P54_Valid; + S_P54_Ready <= S_Out_Ready; + S_Out_Data <= S_P54_Data; + when "110111" => + S_Out_Valid <= S_P55_Valid; + S_P55_Ready <= S_Out_Ready; + S_Out_Data <= S_P55_Data; + when "111000" => + S_Out_Valid <= S_P56_Valid; + S_P56_Ready <= S_Out_Ready; + S_Out_Data <= S_P56_Data; + when "111001" => + S_Out_Valid <= S_P57_Valid; + S_P57_Ready <= S_Out_Ready; + S_Out_Data <= S_P57_Data; + when "111010" => + S_Out_Valid <= S_P58_Valid; + S_P58_Ready <= S_Out_Ready; + S_Out_Data <= S_P58_Data; + when "111011" => + S_Out_Valid <= S_P59_Valid; + S_P59_Ready <= S_Out_Ready; + S_Out_Data <= S_P59_Data; + when "111100" => + S_Out_Valid <= S_P60_Valid; + S_P60_Ready <= S_Out_Ready; + S_Out_Data <= S_P60_Data; + when "111101" => + S_Out_Valid <= S_P61_Valid; + S_P61_Ready <= S_Out_Ready; + S_Out_Data <= S_P61_Data; + when "111110" => + S_Out_Valid <= S_P62_Valid; + S_P62_Ready <= S_Out_Ready; + S_Out_Data <= S_P62_Data; + when "111111" => + S_Out_Valid <= S_P63_Valid; + S_P63_Ready <= S_Out_Ready; + S_Out_Data <= S_P63_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 6, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/build/AXI_Handshaking_Scheduler_8.vhdl b/build/AXI_Handshaking_Scheduler_8.vhdl new file mode 100644 index 0000000..b77a6a9 --- /dev/null +++ b/build/AXI_Handshaking_Scheduler_8.vhdl @@ -0,0 +1,481 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_8 is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + --@ @virtualbus P0 @dir in P0 interface + I_P0_Valid : in std_logic := '0'; + O_P0_Ready : out std_logic := '0'; + I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P1 @dir in P1 interface + I_P1_Valid : in std_logic := '0'; + O_P1_Ready : out std_logic := '0'; + I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P2 @dir in P2 interface + I_P2_Valid : in std_logic := '0'; + O_P2_Ready : out std_logic := '0'; + I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P3 @dir in P3 interface + I_P3_Valid : in std_logic := '0'; + O_P3_Ready : out std_logic := '0'; + I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P4 @dir in P4 interface + I_P4_Valid : in std_logic := '0'; + O_P4_Ready : out std_logic := '0'; + I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P5 @dir in P5 interface + I_P5_Valid : in std_logic := '0'; + O_P5_Ready : out std_logic := '0'; + I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P6 @dir in P6 interface + I_P6_Valid : in std_logic := '0'; + O_P6_Ready : out std_logic := '0'; + I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + --@ @virtualbus P7 @dir in P7 interface + I_P7_Valid : in std_logic := '0'; + O_P7_Ready : out std_logic := '0'; + I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector(2 downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_8; + +architecture Rtl of AXI_Handshaking_Scheduler_8 is + signal R_SelectRotator : unsigned(2 downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned(2 downto 0) := (others => '0'); + + signal C_Select : std_logic_vector(7 downto 0) := (others => '0'); + signal C_Code : std_logic_vector(2 downto 0) := (others => '0'); + signal R_Code : std_logic_vector(2 downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector(2 downto 0) := (others => '0'); + + signal S_P0_InBufferEnable : std_logic := '0'; + signal S_P0_Ready : std_logic := '0'; + signal S_P0_Valid : std_logic := '0'; + signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P1_InBufferEnable : std_logic := '0'; + signal S_P1_Ready : std_logic := '0'; + signal S_P1_Valid : std_logic := '0'; + signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P2_InBufferEnable : std_logic := '0'; + signal S_P2_Ready : std_logic := '0'; + signal S_P2_Valid : std_logic := '0'; + signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P3_InBufferEnable : std_logic := '0'; + signal S_P3_Ready : std_logic := '0'; + signal S_P3_Valid : std_logic := '0'; + signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P4_InBufferEnable : std_logic := '0'; + signal S_P4_Ready : std_logic := '0'; + signal S_P4_Valid : std_logic := '0'; + signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P5_InBufferEnable : std_logic := '0'; + signal S_P5_Ready : std_logic := '0'; + signal S_P5_Valid : std_logic := '0'; + signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P6_InBufferEnable : std_logic := '0'; + signal S_P6_Ready : std_logic := '0'; + signal S_P6_Valid : std_logic := '0'; + signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_P7_InBufferEnable : std_logic := '0'; + signal S_P7_Ready : std_logic := '0'; + signal S_P7_Valid : std_logic := '0'; + signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector(2 downto 0) := (others => '0'); +begin + + I_P0_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P0_InBufferEnable, + I_Valid => I_P0_Valid, + O_Ready => O_P0_Ready, + O_Valid => S_P0_Valid, + I_Ready => S_P0_Ready + ); + + I_P0_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P0_InBufferEnable, + I_Data => I_P0_Data, + O_Data => S_P0_Data + ); + I_P1_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P1_InBufferEnable, + I_Valid => I_P1_Valid, + O_Ready => O_P1_Ready, + O_Valid => S_P1_Valid, + I_Ready => S_P1_Ready + ); + + I_P1_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P1_InBufferEnable, + I_Data => I_P1_Data, + O_Data => S_P1_Data + ); + I_P2_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P2_InBufferEnable, + I_Valid => I_P2_Valid, + O_Ready => O_P2_Ready, + O_Valid => S_P2_Valid, + I_Ready => S_P2_Ready + ); + + I_P2_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P2_InBufferEnable, + I_Data => I_P2_Data, + O_Data => S_P2_Data + ); + I_P3_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P3_InBufferEnable, + I_Valid => I_P3_Valid, + O_Ready => O_P3_Ready, + O_Valid => S_P3_Valid, + I_Ready => S_P3_Ready + ); + + I_P3_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P3_InBufferEnable, + I_Data => I_P3_Data, + O_Data => S_P3_Data + ); + I_P4_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P4_InBufferEnable, + I_Valid => I_P4_Valid, + O_Ready => O_P4_Ready, + O_Valid => S_P4_Valid, + I_Ready => S_P4_Ready + ); + + I_P4_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P4_InBufferEnable, + I_Data => I_P4_Data, + O_Data => S_P4_Data + ); + I_P5_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P5_InBufferEnable, + I_Valid => I_P5_Valid, + O_Ready => O_P5_Ready, + O_Valid => S_P5_Valid, + I_Ready => S_P5_Ready + ); + + I_P5_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P5_InBufferEnable, + I_Data => I_P5_Data, + O_Data => S_P5_Data + ); + I_P6_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P6_InBufferEnable, + I_Valid => I_P6_Valid, + O_Ready => O_P6_Ready, + O_Valid => S_P6_Valid, + I_Ready => S_P6_Ready + ); + + I_P6_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P6_InBufferEnable, + I_Data => I_P6_Data, + O_Data => S_P6_Data + ); + I_P7_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P7_InBufferEnable, + I_Valid => I_P7_Valid, + O_Ready => O_P7_Ready, + O_Valid => S_P7_Valid, + I_Ready => S_P7_Ready + ); + + I_P7_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P7_InBufferEnable, + I_Data => I_P7_Data, + O_Data => S_P7_Data + ); + + I_PriorityEncoder_8 : entity work.PriorityEncoder_8 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid) + begin + case R_SelectRotator is when "000" => + C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid; + when "001" => + C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid; + when "010" => + C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid; + when "011" => + C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid; + when "100" => + C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid; + when "101" => + C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid; + when "110" => + C_Select <= S_P6_Valid & S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid; + when "111" => + C_Select <= S_P7_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid; + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_Out_Ready) + begin + S_Out_Valid <= '0'; + S_P0_Ready <= '0'; + S_P1_Ready <= '0'; + S_P2_Ready <= '0'; + S_P3_Ready <= '0'; + S_P4_Ready <= '0'; + S_P5_Ready <= '0'; + S_P6_Ready <= '0'; + S_P7_Ready <= '0'; + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is when "000" => + S_Out_Valid <= S_P0_Valid; + S_P0_Ready <= S_Out_Ready; + S_Out_Data <= S_P0_Data; + when "001" => + S_Out_Valid <= S_P1_Valid; + S_P1_Ready <= S_Out_Ready; + S_Out_Data <= S_P1_Data; + when "010" => + S_Out_Valid <= S_P2_Valid; + S_P2_Ready <= S_Out_Ready; + S_Out_Data <= S_P2_Data; + when "011" => + S_Out_Valid <= S_P3_Valid; + S_P3_Ready <= S_Out_Ready; + S_Out_Data <= S_P3_Data; + when "100" => + S_Out_Valid <= S_P4_Valid; + S_P4_Ready <= S_Out_Ready; + S_Out_Data <= S_P4_Data; + when "101" => + S_Out_Valid <= S_P5_Valid; + S_P5_Ready <= S_Out_Ready; + S_Out_Data <= S_P5_Data; + when "110" => + S_Out_Valid <= S_P6_Valid; + S_P6_Ready <= S_Out_Ready; + S_Out_Data <= S_P6_Data; + when "111" => + S_Out_Valid <= S_P7_Valid; + S_P7_Ready <= S_Out_Ready; + S_Out_Data <= S_P7_Data; + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => 3, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture; diff --git a/gen.py b/gen.py new file mode 100644 index 0000000..588ebcc --- /dev/null +++ b/gen.py @@ -0,0 +1,55 @@ +import math +import os +import argparse +from jinja2 import Environment, FileSystemLoader, TemplateError + +# === Argument-Parser === +def parse_args(): + parser = argparse.ArgumentParser( + description="Generiert ein VHDL-Modul für einen AXI Handshaking Scheduler mit einer wählbaren Anzahl an Ports (nur 2^n bis max. 64 erlaubt)." + ) + parser.add_argument( + "--ports", "-p", + type=int, + required=True, + help="Anzahl der Ports (z. B. 2, 4, 8, 16, 32, 64)" + ) + return parser.parse_args() + +# === Validierung === +def is_power_of_two(n): + return n > 0 and (n & (n - 1)) == 0 + +def validate_ports(n): + if not is_power_of_two(n) or n > 64: + raise ValueError("❌ Fehler: --ports muss eine Zweierpotenz ≤ 64 sein (z. B. 2, 4, 8, 16, 32, 64).") + +# === Main === +def main(): + args = parse_args() + num_ports = args.ports + validate_ports(num_ports) + + TEMPLATE_DIR = "./template" + TEMPLATE_FILE = "AXI-HS-Scheduler_n.vhd.j2" + OUTPUT_DIR = "./build" + + env = Environment( + loader=FileSystemLoader(TEMPLATE_DIR), + trim_blocks=True, + lstrip_blocks=True + ) + + template = env.get_template(TEMPLATE_FILE) + rendered = template.render(num_ports=num_ports) + + os.makedirs(OUTPUT_DIR, exist_ok=True) + outfile = os.path.join(OUTPUT_DIR, f"AXI_Handshaking_Scheduler_{num_ports}.vhdl") + + with open(outfile, "w") as f: + f.write(rendered) + + print(f"✔️ Generiert: {outfile}") + +if __name__ == "__main__": + main() diff --git a/src/PriorityEncoders.vhd b/src/PriorityEncoders.vhd new file mode 100644 index 0000000..0bfd09b --- /dev/null +++ b/src/PriorityEncoders.vhd @@ -0,0 +1,345 @@ +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (2 to 1 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 1-bit output code. +entity PriorityEncoder_2 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(1 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(0 downto 0) := (others => '0') + ); +end entity PriorityEncoder_2; + +architecture Combinatoric of PriorityEncoder_2 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(0 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; +begin + C_Code <= "0" when I_Select(1) = '1' else + "1" when I_Select(0) = '1' else + "-"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (4 to 2 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 2-bit output code. +entity PriorityEncoder_4 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(3 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(1 downto 0) := (others => '0') + ); +end entity PriorityEncoder_4; + +architecture Combinatoric of PriorityEncoder_4 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(1 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; +begin + C_Code <= "00" when I_Select(3) = '1' else + "01" when I_Select(2) = '1' else + "10" when I_Select(1) = '1' else + "11" when I_Select(0) = '1' else + "--"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (8 to 3 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 3-bit output code. +entity PriorityEncoder_8 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(7 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(2 downto 0) := (others => '0') + ); +end entity PriorityEncoder_8; + +architecture Combinatoric of PriorityEncoder_8 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(2 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; +begin + C_Code <= "000" when I_Select(7) = '1' else + "001" when I_Select(6) = '1' else + "010" when I_Select(5) = '1' else + "011" when I_Select(4) = '1' else + "100" when I_Select(3) = '1' else + "101" when I_Select(2) = '1' else + "110" when I_Select(1) = '1' else + "111" when I_Select(0) = '1' else + "---"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (16 to 4 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 4-bit output code. +entity PriorityEncoder_16 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(15 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(3 downto 0) := (others => '0') + ); +end entity PriorityEncoder_16; + +architecture Combinatoric of PriorityEncoder_16 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(3 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; +begin + C_Code <= "0000" when I_Select(15) = '1' else + "0001" when I_Select(14) = '1' else + "0010" when I_Select(13) = '1' else + "0011" when I_Select(12) = '1' else + "0100" when I_Select(11) = '1' else + "0101" when I_Select(10) = '1' else + "0110" when I_Select(9) = '1' else + "0111" when I_Select(8) = '1' else + "1000" when I_Select(7) = '1' else + "1001" when I_Select(6) = '1' else + "1010" when I_Select(5) = '1' else + "1011" when I_Select(4) = '1' else + "1100" when I_Select(3) = '1' else + "1101" when I_Select(2) = '1' else + "1110" when I_Select(1) = '1' else + "1111" when I_Select(0) = '1' else + "----"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (32 to 5 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 5-bit output code. +entity PriorityEncoder_32 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(31 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(4 downto 0) := (others => '0') + ); +end entity PriorityEncoder_32; + +architecture Combinatoric of PriorityEncoder_32 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(4 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; + +begin + C_Code <= "00000" when I_Select(31) = '1' else + "00001" when I_Select(30) = '1' else + "00010" when I_Select(29) = '1' else + "00011" when I_Select(28) = '1' else + "00100" when I_Select(27) = '1' else + "00101" when I_Select(26) = '1' else + "00110" when I_Select(25) = '1' else + "00111" when I_Select(24) = '1' else + "01000" when I_Select(23) = '1' else + "01001" when I_Select(22) = '1' else + "01010" when I_Select(21) = '1' else + "01011" when I_Select(20) = '1' else + "01100" when I_Select(19) = '1' else + "01101" when I_Select(18) = '1' else + "01110" when I_Select(17) = '1' else + "01111" when I_Select(16) = '1' else + "10000" when I_Select(15) = '1' else + "10001" when I_Select(14) = '1' else + "10010" when I_Select(13) = '1' else + "10011" when I_Select(12) = '1' else + "10100" when I_Select(11) = '1' else + "10101" when I_Select(10) = '1' else + "10110" when I_Select(9) = '1' else + "10111" when I_Select(8) = '1' else + "11000" when I_Select(7) = '1' else + "11001" when I_Select(6) = '1' else + "11010" when I_Select(5) = '1' else + "11011" when I_Select(4) = '1' else + "11100" when I_Select(3) = '1' else + "11101" when I_Select(2) = '1' else + "11110" when I_Select(1) = '1' else + "11111" when I_Select(0) = '1' else + "-----"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +--@ Priority Encoder (64 to 6 bits) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 6-bit output code. +entity PriorityEncoder_64 is + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(63 downto 0) := (others => '0'); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(5 downto 0) := (others => '0') + ); +end entity PriorityEncoder_64; + +architecture Combinatoric of PriorityEncoder_64 is + --@ Internal signal to hold the encoded output. + signal C_Code : std_logic_vector(5 downto 0); + + --@ Attribute to force the synthesis tool (XST, old Parser) to treat this as a combinatorial signal. + attribute PRIORITY_EXTRACT : string; + attribute PRIORITY_EXTRACT of C_Code : signal is "force"; + +begin + C_Code <= "000000" when I_Select(63) = '1' else + "000001" when I_Select(62) = '1' else + "000010" when I_Select(61) = '1' else + "000011" when I_Select(60) = '1' else + "000100" when I_Select(59) = '1' else + "000101" when I_Select(58) = '1' else + "000110" when I_Select(57) = '1' else + "000111" when I_Select(56) = '1' else + "001000" when I_Select(55) = '1' else + "001001" when I_Select(54) = '1' else + "001010" when I_Select(53) = '1' else + "001011" when I_Select(52) = '1' else + "001100" when I_Select(51) = '1' else + "001101" when I_Select(50) = '1' else + "001110" when I_Select(49) = '1' else + "001111" when I_Select(48) = '1' else + "010000" when I_Select(47) = '1' else + "010001" when I_Select(46) = '1' else + "010010" when I_Select(45) = '1' else + "010011" when I_Select(44) = '1' else + "010100" when I_Select(43) = '1' else + "010101" when I_Select(42) = '1' else + "010110" when I_Select(41) = '1' else + "010111" when I_Select(40) = '1' else + "011000" when I_Select(39) = '1' else + "011001" when I_Select(38) = '1' else + "011010" when I_Select(37) = '1' else + "011011" when I_Select(36) = '1' else + "011100" when I_Select(35) = '1' else + "011101" when I_Select(34) = '1' else + "011110" when I_Select(33) = '1' else + "011111" when I_Select(32) = '1' else + "100000" when I_Select(31) = '1' else + "100001" when I_Select(30) = '1' else + "100010" when I_Select(29) = '1' else + "100011" when I_Select(28) = '1' else + "100100" when I_Select(27) = '1' else + "100101" when I_Select(26) = '1' else + "100110" when I_Select(25) = '1' else + "100111" when I_Select(24) = '1' else + "101000" when I_Select(23) = '1' else + "101001" when I_Select(22) = '1' else + "101010" when I_Select(21) = '1' else + "101011" when I_Select(20) = '1' else + "101100" when I_Select(19) = '1' else + "101101" when I_Select(18) = '1' else + "101110" when I_Select(17) = '1' else + "101111" when I_Select(16) = '1' else + "110000" when I_Select(15) = '1' else + "110001" when I_Select(14) = '1' else + "110010" when I_Select(13) = '1' else + "110011" when I_Select(12) = '1' else + "110100" when I_Select(11) = '1' else + "110101" when I_Select(10) = '1' else + "110110" when I_Select(9) = '1' else + "110111" when I_Select(8) = '1' else + "111000" when I_Select(7) = '1' else + "111001" when I_Select(6) = '1' else + "111010" when I_Select(5) = '1' else + "111011" when I_Select(4) = '1' else + "111100" when I_Select(3) = '1' else + "111101" when I_Select(2) = '1' else + "111110" when I_Select(1) = '1' else + "111111" when I_Select(0) = '1' else + "------"; + + O_Code <= C_Code; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +--@ Priority Encoder (Generic) +--@ This is a combinatorial priority encoder that encodes the highest priority +--@ bit in the input vector to a 6-bit output code. +entity PriorityEncoder_G is + generic ( + --@ Code width with minimum 2 bits and maximum 6 bits. + G_CodeWidth : integer := 6 + ); + port ( + --@ Input vector to be encoded. + --@ The most significant bit has the highest priority. + I_Select : in std_logic_vector(2 ** G_CodeWidth - 1 downto 0); + --@ Output code. + --@ The output code is the index of the highest priority bit in the input vector. + O_Code : out std_logic_vector(G_CodeWidth - 1 downto 0) + ); +end entity PriorityEncoder_G; + +architecture Combinatoric of PriorityEncoder_G is + signal C_Select : std_logic_vector(63 downto 0) := (others => '-'); + signal C_Code : std_logic_vector(5 downto 0) := (others => '-'); +begin + + entity_inst : entity work.PriorityEncoder_64 + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + C_Select(G_CodeWidth * 2 - 1 downto 0) <= I_Select; + O_Code <= C_Code(G_CodeWidth - 1 downto 0); +end architecture; diff --git a/tb/Scheduler_tb.vhd b/tb/Scheduler_tb.vhd new file mode 100644 index 0000000..a5e0ee0 --- /dev/null +++ b/tb/Scheduler_tb.vhd @@ -0,0 +1,210 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use std.env.stop; + +entity Scheduler_tb is +end entity Scheduler_tb; + +architecture Bench of Scheduler_tb is + -- Clock period + constant K_CLKPeriod : time := 10 ns; + + -- Generics + constant G_DataWidth : integer := 32; + -- Ports + signal I_CLK : std_logic; + signal I_CE : std_logic := '1'; + signal I_RST : std_logic := '0'; + signal I_P0_Valid : std_logic := '0'; + signal O_P0_Ready : std_logic := '0'; + signal I_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal I_P1_Valid : std_logic := '0'; + signal O_P1_Ready : std_logic := '0'; + signal I_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal I_P2_Valid : std_logic := '0'; + signal O_P2_Ready : std_logic := '0'; + signal I_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal I_P3_Valid : std_logic := '0'; + signal O_P3_Ready : std_logic := '0'; + signal I_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal O_Out_Valid : std_logic := '0'; + signal I_Out_Ready : std_logic := '0'; + signal O_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal O_Out_Address : std_logic_vector(1 downto 0) := (others => '0'); + + signal TestDone : boolean := false; +begin + + ClockProc : process + begin + while TestDone = false loop + I_CLK <= '0'; + wait for K_CLKPeriod / 2; + I_CLK <= '1'; + wait for K_CLKPeriod / 2; + end loop; + + I_CLK <= '0'; + stop(0); + wait; + end process; + + i_AXI_Handshaking_Scheduler_4 : entity work.AXI_Handshaking_Scheduler_4 + generic map( + G_DataWidth => G_DataWidth + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + I_P0_Valid => I_P0_Valid, + O_P0_Ready => O_P0_Ready, + I_P0_Data => I_P0_Data, + I_P1_Valid => I_P1_Valid, + O_P1_Ready => O_P1_Ready, + I_P1_Data => I_P1_Data, + I_P2_Valid => I_P2_Valid, + O_P2_Ready => O_P2_Ready, + I_P2_Data => I_P2_Data, + I_P3_Valid => I_P3_Valid, + O_P3_Ready => O_P3_Ready, + I_P3_Data => I_P3_Data, + O_Out_Valid => O_Out_Valid, + I_Out_Ready => I_Out_Ready, + O_Out_Data => O_Out_Data, + O_Out_Address => O_Out_Address + ); + + ReceiverProc : process + variable PacketCounter : integer := 0; + begin + I_Out_Ready <= '0'; + wait for 3 * K_CLKPeriod; + + loop + -- Ein paar Takte Ready aktivieren + I_Out_Ready <= '1'; + for i in 0 to 2 loop + wait until rising_edge(I_CLK); + if O_Out_Valid = '1' and I_Out_Ready = '1' then + report "Received packet #" & integer'image(PacketCounter) & + " from address " & integer'image(to_integer(unsigned(O_Out_Address))) & + " with data: " & integer'image(to_integer(unsigned(O_Out_Data))); + + PacketCounter := PacketCounter + 1; + end if; + end loop; + + -- Pausephase + -- I_Out_Ready <= '0'; + -- wait for 1 * K_CLKPeriod; + end loop; + end process; + + -- Sender 0: sendet 1 Paket + Sender0Proc : process (I_CLK) + constant K_MaxCount : integer := 280; + variable V_Counter : integer := 0; + begin + if rising_edge(I_CLK) then + if V_Counter < K_MaxCount then + I_P0_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth)); + I_P0_Valid <= '1'; + if O_P0_Ready = '1' and I_P0_Valid = '1' then + report "Sender 0: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P0_Data))); + V_Counter := V_Counter + 1; + if V_Counter = K_MaxCount then + I_P0_Valid <= '0'; + end if; + end if; + else + if V_Counter = K_MaxCount then + V_Counter := V_Counter + 1; + report "Sender 0: No more packets to send."; + end if; + I_P0_Valid <= '0'; + end if; + end if; + end process; + + -- Sender 1: sendet 1 Paket + Sender1Proc : process (I_CLK) + constant K_MaxCount : integer := 225; + variable V_Counter : integer := 0; + begin + if rising_edge(I_CLK) then + if V_Counter < K_MaxCount then + I_P1_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth)); + I_P1_Valid <= '1'; + if O_P1_Ready = '1' and I_P1_Valid = '1' then + report "Sender 1: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P1_Data))); + V_Counter := V_Counter + 1; + if V_Counter = K_MaxCount then + I_P1_Valid <= '0'; + end if; + end if; + else + if V_Counter = K_MaxCount then + V_Counter := V_Counter + 1; + report "Sender 1: No more packets to send."; + end if; + I_P1_Valid <= '0'; + end if; + end if; + end process; + + -- Sender 2: sendet 1 Paket + Sender2Proc : process (I_CLK) + constant K_MaxCount : integer := 665; + variable V_Counter : integer := 0; + begin + if rising_edge(I_CLK) then + if V_Counter < K_MaxCount then + I_P2_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth)); + I_P2_Valid <= '1'; + if O_P2_Ready = '1' and I_P2_Valid = '1' then + report "Sender 2: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P2_Data))); + V_Counter := V_Counter + 1; + if V_Counter = K_MaxCount then + I_P2_Valid <= '0'; + end if; + end if; + else + if V_Counter = K_MaxCount then + V_Counter := V_Counter + 1; + report "Sender 2: No more packets to send."; + end if; + I_P2_Valid <= '0'; + end if; + end if; + end process; + + -- Sender 3: sendet 1 Paket + Sender3Proc : process (I_CLK) + constant K_MaxCount : integer := 150; + variable V_Counter : integer := 0; + begin + if rising_edge(I_CLK) then + if V_Counter < K_MaxCount then + I_P3_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth)); + I_P3_Valid <= '1'; + if O_P3_Ready = '1' and I_P3_Valid = '1' then + report "Sender 3: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P3_Data))); + V_Counter := V_Counter + 1; + if V_Counter = K_MaxCount then + I_P3_Valid <= '0'; + end if; + end if; + else + if V_Counter = K_MaxCount then + V_Counter := V_Counter + 1; + report "Sender 3: No more packets to send."; + end if; + I_P3_Valid <= '0'; + end if; + end if; + end process; + +end architecture; diff --git a/tb/Scheduler_tb.wcfg b/tb/Scheduler_tb.wcfg new file mode 100644 index 0000000..0f30d70 --- /dev/null +++ b/tb/Scheduler_tb.wcfg @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + i_clk + i_clk + + + i_ce + i_ce + + + i_rst + i_rst + + + i_p0_valid + i_p0_valid + + + o_p0_ready + o_p0_ready + + + i_p0_data[31:0] + i_p0_data[31:0] + + + i_p1_valid + i_p1_valid + + + o_p1_ready + o_p1_ready + + + i_p1_data[31:0] + i_p1_data[31:0] + + + i_p2_valid + i_p2_valid + + + o_p2_ready + o_p2_ready + + + i_p2_data[31:0] + i_p2_data[31:0] + + + i_p3_valid + i_p3_valid + + + o_p3_ready + o_p3_ready + + + i_p3_data[31:0] + i_p3_data[31:0] + + + o_out_valid + o_out_valid + + + i_out_ready + i_out_ready + + + o_out_data[31:0] + o_out_data[31:0] + + + o_out_address[1:0] + o_out_address[1:0] + UNSIGNEDDECRADIX + + + Intern + label + + r_counter[1:0] + r_counter[1:0] + + + c_select[3:0] + c_select[3:0] + + + c_code[1:0] + c_code[1:0] + BINARYRADIX + + + c_codereverse[1:0] + c_codereverse[1:0] + UNSIGNEDDECRADIX + + + + PE + label + + i_select[3:0] + i_select[3:0] + + + o_code[1:0] + o_code[1:0] + + + c_code[1:0] + c_code[1:0] + + + diff --git a/template/AXI-HS-Scheduler_n.vhd.j2 b/template/AXI-HS-Scheduler_n.vhd.j2 new file mode 100644 index 0000000..7058bd9 --- /dev/null +++ b/template/AXI-HS-Scheduler_n.vhd.j2 @@ -0,0 +1,202 @@ +{% set addr_width = (num_ports - 1).bit_length() %} +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity AXI_Handshaking_Scheduler_{{ num_ports }} is + generic ( + G_DataWidth : integer := 8; + G_InBufferStages : integer := 1; + G_OutBufferStages : integer := 1 + ); + port ( + --@ Clock signal; (**Rising edge** triggered) + I_CLK : in std_logic; + --@ Clock enable signal (**Active high**) + I_CE : in std_logic; + --@ Synchronous reset signal (**Active high**) + I_RST : in std_logic; + + {% for i in range(num_ports) %} + --@ @virtualbus P{{ i }} @dir in P{{ i }} interface + I_P{{ i }}_Valid : in std_logic := '0'; + O_P{{ i }}_Ready : out std_logic := '0'; + I_P{{ i }}_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + --@ @end + {% endfor %} + + --@ @virtualbus Out @dir out Output interface + O_Out_Valid : out std_logic := '0'; + I_Out_Ready : in std_logic := '0'; + O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + O_Out_Address : out std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0') + --@ @end + ); +end entity AXI_Handshaking_Scheduler_{{ num_ports }}; + +architecture Rtl of AXI_Handshaking_Scheduler_{{ num_ports }} is + signal R_SelectRotator : unsigned({{ addr_width - 1 }} downto 0) := (others => '0'); + signal R1_SelectRotator : unsigned({{ addr_width - 1 }} downto 0) := (others => '0'); + + signal C_Select : std_logic_vector({{ num_ports - 1 }} downto 0) := (others => '0'); + signal C_Code : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0'); + signal R_Code : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0'); + signal C_CodeUnrotated : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0'); + + {% for i in range(num_ports) %} + signal S_P{{ i }}_InBufferEnable : std_logic := '0'; + signal S_P{{ i }}_Ready : std_logic := '0'; + signal S_P{{ i }}_Valid : std_logic := '0'; + signal S_P{{ i }}_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + {% endfor %} + + signal S_OutBufferEnable : std_logic := '0'; + signal S_Out_Ready : std_logic := '0'; + signal S_Out_Valid : std_logic := '0'; + signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); + signal S_Out_Address : std_logic_vector({{ addr_width - 1 }} downto 0) := (others => '0'); +begin + + {% for i in range(num_ports) %} + I_P{{ i }}_InBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_InBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_P{{ i }}_InBufferEnable, + I_Valid => I_P{{ i }}_Valid, + O_Ready => O_P{{ i }}_Ready, + O_Valid => S_P{{ i }}_Valid, + I_Ready => S_P{{ i }}_Ready + ); + + I_P{{ i }}_InBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_InBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "forward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_P{{ i }}_InBufferEnable, + I_Data => I_P{{ i }}_Data, + O_Data => S_P{{ i }}_Data + ); + {% endfor %} + + I_PriorityEncoder_{{ num_ports }} : entity work.PriorityEncoder_{{ num_ports }} + port map( + I_Select => C_Select, + O_Code => C_Code + ); + + P_SelectMux : process (R_SelectRotator + {%- for i in range(num_ports) %}, S_P{{ i }}_Valid{% endfor %}) + begin + case R_SelectRotator is + {%- for r in range(num_ports) %} + when "{{ '{:0{}b}'.format(r, addr_width) }}" => + C_Select <= + {%- for i in range(num_ports) -%} + S_P{{ (i + r) % num_ports }}_Valid{% if not loop.last %} & {% endif %} + {%- endfor %}; + {% endfor %} + when others => + C_Select <= (others => '-'); + end case; + end process; + + P_CodeUnrotating : process (R_Code, R1_SelectRotator) + begin + C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator); + end process; + + P_OutMux : process ( + C_CodeUnrotated + {%- for i in range(num_ports) %}, S_P{{ i }}_Data{% endfor %} + {%- for i in range(num_ports) %}, S_P{{ i }}_Valid{% endfor %} + , S_Out_Ready) + begin + S_Out_Valid <= '0'; + {%- for i in range(num_ports) %} + S_P{{ i }}_Ready <= '0'; + {%- endfor %} + S_Out_Data <= (others => '-'); + S_Out_Address <= C_CodeUnrotated; + + case C_CodeUnrotated is + {%- for i in range(num_ports) %} + when "{{ '{:0{}b}'.format(i, addr_width) }}" => + S_Out_Valid <= S_P{{ i }}_Valid; + S_P{{ i }}_Ready <= S_Out_Ready; + S_Out_Data <= S_P{{ i }}_Data; + {%- endfor %} + when others => + S_Out_Address <= (others => '-'); + end case; + end process; + + P_SelectRotator : process (I_CLK) + begin + if rising_edge(I_CLK) then + if I_CE = '1' then + if I_RST = '1' then + R_SelectRotator <= (others => '0'); + R1_SelectRotator <= (others => '0'); + R_Code <= (others => '0'); + else + R1_SelectRotator <= R_SelectRotator; + R_Code <= C_Code; + if I_Out_Ready = '1' then + R_SelectRotator <= unsigned(C_CodeUnrotated) + 1; + end if; + end if; + end if; + end if; + end process P_SelectRotator; + + I_OutBufferCtrl : entity work.PipelineController + generic map( + G_PipelineStages => G_OutBufferStages + ) + port map( + I_CLK => I_CLK, + I_CE => I_CE, + I_RST => I_RST, + O_Enable => S_OutBufferEnable, + I_Valid => S_Out_Valid, + O_Ready => S_Out_Ready, + O_Valid => O_Out_Valid, + I_Ready => I_Out_Ready + ); + + I_OutDataBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => G_DataWidth, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Data, + O_Data => O_Out_Data + ); + + I_OutAddressBuffer : entity work.PipelineRegister + generic map( + G_PipelineStages => G_OutBufferStages, + G_Width => {{ addr_width }}, + G_RegisterBalancing => "backward" + ) + port map( + I_CLK => I_CLK, + I_Enable => S_OutBufferEnable, + I_Data => S_Out_Address, + O_Data => O_Out_Address + ); +end architecture;