826 lines
32 KiB
VHDL
826 lines
32 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity AXI_Handshaking_Scheduler_16 is
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generic (
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G_DataWidth : integer := 8;
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G_InBufferStages : integer := 1;
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G_OutBufferStages : integer := 1
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);
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port (
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--@ Clock signal; (**Rising edge** triggered)
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I_CLK : in std_logic;
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--@ Clock enable signal (**Active high**)
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I_CE : in std_logic;
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--@ Synchronous reset signal (**Active high**)
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I_RST : in std_logic;
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--@ @virtualbus P0 @dir in P0 interface
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I_P0_Valid : in std_logic := '0';
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O_P0_Ready : out std_logic := '0';
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I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P1 @dir in P1 interface
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I_P1_Valid : in std_logic := '0';
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O_P1_Ready : out std_logic := '0';
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I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P2 @dir in P2 interface
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I_P2_Valid : in std_logic := '0';
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O_P2_Ready : out std_logic := '0';
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I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P3 @dir in P3 interface
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I_P3_Valid : in std_logic := '0';
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O_P3_Ready : out std_logic := '0';
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I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P4 @dir in P4 interface
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I_P4_Valid : in std_logic := '0';
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O_P4_Ready : out std_logic := '0';
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I_P4_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P5 @dir in P5 interface
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I_P5_Valid : in std_logic := '0';
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O_P5_Ready : out std_logic := '0';
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I_P5_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P6 @dir in P6 interface
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I_P6_Valid : in std_logic := '0';
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O_P6_Ready : out std_logic := '0';
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I_P6_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P7 @dir in P7 interface
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I_P7_Valid : in std_logic := '0';
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O_P7_Ready : out std_logic := '0';
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I_P7_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P8 @dir in P8 interface
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I_P8_Valid : in std_logic := '0';
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O_P8_Ready : out std_logic := '0';
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I_P8_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P9 @dir in P9 interface
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I_P9_Valid : in std_logic := '0';
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O_P9_Ready : out std_logic := '0';
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I_P9_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P10 @dir in P10 interface
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I_P10_Valid : in std_logic := '0';
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O_P10_Ready : out std_logic := '0';
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I_P10_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P11 @dir in P11 interface
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I_P11_Valid : in std_logic := '0';
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O_P11_Ready : out std_logic := '0';
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I_P11_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P12 @dir in P12 interface
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I_P12_Valid : in std_logic := '0';
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O_P12_Ready : out std_logic := '0';
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I_P12_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P13 @dir in P13 interface
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I_P13_Valid : in std_logic := '0';
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O_P13_Ready : out std_logic := '0';
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I_P13_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P14 @dir in P14 interface
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I_P14_Valid : in std_logic := '0';
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O_P14_Ready : out std_logic := '0';
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I_P14_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P15 @dir in P15 interface
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I_P15_Valid : in std_logic := '0';
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O_P15_Ready : out std_logic := '0';
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I_P15_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus Out @dir out Output interface
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O_Out_Valid : out std_logic := '0';
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I_Out_Ready : in std_logic := '0';
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O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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O_Out_Address : out std_logic_vector(3 downto 0) := (others => '0')
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--@ @end
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);
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end entity AXI_Handshaking_Scheduler_16;
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architecture Rtl of AXI_Handshaking_Scheduler_16 is
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signal R_SelectRotator : unsigned(3 downto 0) := (others => '0');
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signal R1_SelectRotator : unsigned(3 downto 0) := (others => '0');
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signal C_Select : std_logic_vector(15 downto 0) := (others => '0');
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signal C_Code : std_logic_vector(3 downto 0) := (others => '0');
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signal R_Code : std_logic_vector(3 downto 0) := (others => '0');
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signal C_CodeUnrotated : std_logic_vector(3 downto 0) := (others => '0');
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signal S_P0_InBufferEnable : std_logic := '0';
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signal S_P0_Ready : std_logic := '0';
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signal S_P0_Valid : std_logic := '0';
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signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P1_InBufferEnable : std_logic := '0';
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signal S_P1_Ready : std_logic := '0';
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signal S_P1_Valid : std_logic := '0';
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signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P2_InBufferEnable : std_logic := '0';
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signal S_P2_Ready : std_logic := '0';
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signal S_P2_Valid : std_logic := '0';
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signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P3_InBufferEnable : std_logic := '0';
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signal S_P3_Ready : std_logic := '0';
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signal S_P3_Valid : std_logic := '0';
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signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P4_InBufferEnable : std_logic := '0';
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signal S_P4_Ready : std_logic := '0';
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signal S_P4_Valid : std_logic := '0';
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signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P5_InBufferEnable : std_logic := '0';
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signal S_P5_Ready : std_logic := '0';
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signal S_P5_Valid : std_logic := '0';
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signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P6_InBufferEnable : std_logic := '0';
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signal S_P6_Ready : std_logic := '0';
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signal S_P6_Valid : std_logic := '0';
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signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P7_InBufferEnable : std_logic := '0';
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signal S_P7_Ready : std_logic := '0';
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signal S_P7_Valid : std_logic := '0';
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signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P8_InBufferEnable : std_logic := '0';
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signal S_P8_Ready : std_logic := '0';
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signal S_P8_Valid : std_logic := '0';
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signal S_P8_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P9_InBufferEnable : std_logic := '0';
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signal S_P9_Ready : std_logic := '0';
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signal S_P9_Valid : std_logic := '0';
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signal S_P9_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P10_InBufferEnable : std_logic := '0';
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signal S_P10_Ready : std_logic := '0';
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signal S_P10_Valid : std_logic := '0';
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signal S_P10_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P11_InBufferEnable : std_logic := '0';
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signal S_P11_Ready : std_logic := '0';
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signal S_P11_Valid : std_logic := '0';
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signal S_P11_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P12_InBufferEnable : std_logic := '0';
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signal S_P12_Ready : std_logic := '0';
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signal S_P12_Valid : std_logic := '0';
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signal S_P12_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P13_InBufferEnable : std_logic := '0';
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signal S_P13_Ready : std_logic := '0';
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signal S_P13_Valid : std_logic := '0';
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signal S_P13_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P14_InBufferEnable : std_logic := '0';
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signal S_P14_Ready : std_logic := '0';
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signal S_P14_Valid : std_logic := '0';
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signal S_P14_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P15_InBufferEnable : std_logic := '0';
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signal S_P15_Ready : std_logic := '0';
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signal S_P15_Valid : std_logic := '0';
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signal S_P15_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_OutBufferEnable : std_logic := '0';
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signal S_Out_Ready : std_logic := '0';
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signal S_Out_Valid : std_logic := '0';
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signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_Out_Address : std_logic_vector(3 downto 0) := (others => '0');
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begin
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I_P0_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P0_InBufferEnable,
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I_Valid => I_P0_Valid,
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O_Ready => O_P0_Ready,
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O_Valid => S_P0_Valid,
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I_Ready => S_P0_Ready
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);
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I_P0_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P0_InBufferEnable,
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I_Data => I_P0_Data,
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O_Data => S_P0_Data
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);
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I_P1_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P1_InBufferEnable,
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I_Valid => I_P1_Valid,
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O_Ready => O_P1_Ready,
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O_Valid => S_P1_Valid,
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I_Ready => S_P1_Ready
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);
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I_P1_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P1_InBufferEnable,
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I_Data => I_P1_Data,
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O_Data => S_P1_Data
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);
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I_P2_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P2_InBufferEnable,
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I_Valid => I_P2_Valid,
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O_Ready => O_P2_Ready,
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O_Valid => S_P2_Valid,
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I_Ready => S_P2_Ready
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);
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I_P2_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P2_InBufferEnable,
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I_Data => I_P2_Data,
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O_Data => S_P2_Data
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);
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I_P3_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P3_InBufferEnable,
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I_Valid => I_P3_Valid,
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O_Ready => O_P3_Ready,
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O_Valid => S_P3_Valid,
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I_Ready => S_P3_Ready
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);
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I_P3_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P3_InBufferEnable,
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I_Data => I_P3_Data,
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O_Data => S_P3_Data
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);
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I_P4_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P4_InBufferEnable,
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I_Valid => I_P4_Valid,
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O_Ready => O_P4_Ready,
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O_Valid => S_P4_Valid,
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I_Ready => S_P4_Ready
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);
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I_P4_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P4_InBufferEnable,
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I_Data => I_P4_Data,
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O_Data => S_P4_Data
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);
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I_P5_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P5_InBufferEnable,
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I_Valid => I_P5_Valid,
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O_Ready => O_P5_Ready,
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O_Valid => S_P5_Valid,
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I_Ready => S_P5_Ready
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);
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I_P5_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P5_InBufferEnable,
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I_Data => I_P5_Data,
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O_Data => S_P5_Data
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);
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I_P6_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P6_InBufferEnable,
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I_Valid => I_P6_Valid,
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O_Ready => O_P6_Ready,
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O_Valid => S_P6_Valid,
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I_Ready => S_P6_Ready
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);
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I_P6_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P6_InBufferEnable,
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I_Data => I_P6_Data,
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O_Data => S_P6_Data
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);
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I_P7_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P7_InBufferEnable,
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I_Valid => I_P7_Valid,
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O_Ready => O_P7_Ready,
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O_Valid => S_P7_Valid,
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I_Ready => S_P7_Ready
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);
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I_P7_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P7_InBufferEnable,
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I_Data => I_P7_Data,
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O_Data => S_P7_Data
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);
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I_P8_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P8_InBufferEnable,
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I_Valid => I_P8_Valid,
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O_Ready => O_P8_Ready,
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O_Valid => S_P8_Valid,
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I_Ready => S_P8_Ready
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);
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I_P8_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P8_InBufferEnable,
|
|
I_Data => I_P8_Data,
|
|
O_Data => S_P8_Data
|
|
);
|
|
I_P9_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P9_InBufferEnable,
|
|
I_Valid => I_P9_Valid,
|
|
O_Ready => O_P9_Ready,
|
|
O_Valid => S_P9_Valid,
|
|
I_Ready => S_P9_Ready
|
|
);
|
|
|
|
I_P9_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P9_InBufferEnable,
|
|
I_Data => I_P9_Data,
|
|
O_Data => S_P9_Data
|
|
);
|
|
I_P10_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P10_InBufferEnable,
|
|
I_Valid => I_P10_Valid,
|
|
O_Ready => O_P10_Ready,
|
|
O_Valid => S_P10_Valid,
|
|
I_Ready => S_P10_Ready
|
|
);
|
|
|
|
I_P10_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P10_InBufferEnable,
|
|
I_Data => I_P10_Data,
|
|
O_Data => S_P10_Data
|
|
);
|
|
I_P11_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P11_InBufferEnable,
|
|
I_Valid => I_P11_Valid,
|
|
O_Ready => O_P11_Ready,
|
|
O_Valid => S_P11_Valid,
|
|
I_Ready => S_P11_Ready
|
|
);
|
|
|
|
I_P11_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P11_InBufferEnable,
|
|
I_Data => I_P11_Data,
|
|
O_Data => S_P11_Data
|
|
);
|
|
I_P12_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P12_InBufferEnable,
|
|
I_Valid => I_P12_Valid,
|
|
O_Ready => O_P12_Ready,
|
|
O_Valid => S_P12_Valid,
|
|
I_Ready => S_P12_Ready
|
|
);
|
|
|
|
I_P12_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P12_InBufferEnable,
|
|
I_Data => I_P12_Data,
|
|
O_Data => S_P12_Data
|
|
);
|
|
I_P13_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P13_InBufferEnable,
|
|
I_Valid => I_P13_Valid,
|
|
O_Ready => O_P13_Ready,
|
|
O_Valid => S_P13_Valid,
|
|
I_Ready => S_P13_Ready
|
|
);
|
|
|
|
I_P13_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P13_InBufferEnable,
|
|
I_Data => I_P13_Data,
|
|
O_Data => S_P13_Data
|
|
);
|
|
I_P14_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P14_InBufferEnable,
|
|
I_Valid => I_P14_Valid,
|
|
O_Ready => O_P14_Ready,
|
|
O_Valid => S_P14_Valid,
|
|
I_Ready => S_P14_Ready
|
|
);
|
|
|
|
I_P14_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P14_InBufferEnable,
|
|
I_Data => I_P14_Data,
|
|
O_Data => S_P14_Data
|
|
);
|
|
I_P15_InBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_P15_InBufferEnable,
|
|
I_Valid => I_P15_Valid,
|
|
O_Ready => O_P15_Ready,
|
|
O_Valid => S_P15_Valid,
|
|
I_Ready => S_P15_Ready
|
|
);
|
|
|
|
I_P15_InBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_InBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "forward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_P15_InBufferEnable,
|
|
I_Data => I_P15_Data,
|
|
O_Data => S_P15_Data
|
|
);
|
|
|
|
I_PriorityEncoder_16 : entity work.PriorityEncoder_16
|
|
port map(
|
|
I_Select => C_Select,
|
|
O_Code => C_Code
|
|
);
|
|
|
|
P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid)
|
|
begin
|
|
case R_SelectRotator is when "0000" =>
|
|
C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid;
|
|
when "0001" =>
|
|
C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid;
|
|
when "0010" =>
|
|
C_Select <= S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid;
|
|
when "0011" =>
|
|
C_Select <= S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
|
|
when "0100" =>
|
|
C_Select <= S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
|
|
when "0101" =>
|
|
C_Select <= S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid;
|
|
when "0110" =>
|
|
C_Select <= S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid;
|
|
when "0111" =>
|
|
C_Select <= S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid;
|
|
when "1000" =>
|
|
C_Select <= S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid;
|
|
when "1001" =>
|
|
C_Select <= S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid;
|
|
when "1010" =>
|
|
C_Select <= S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid;
|
|
when "1011" =>
|
|
C_Select <= S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid;
|
|
when "1100" =>
|
|
C_Select <= S_P12_Valid & S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid;
|
|
when "1101" =>
|
|
C_Select <= S_P13_Valid & S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid;
|
|
when "1110" =>
|
|
C_Select <= S_P14_Valid & S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid;
|
|
when "1111" =>
|
|
C_Select <= S_P15_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P4_Valid & S_P5_Valid & S_P6_Valid & S_P7_Valid & S_P8_Valid & S_P9_Valid & S_P10_Valid & S_P11_Valid & S_P12_Valid & S_P13_Valid & S_P14_Valid;
|
|
when others =>
|
|
C_Select <= (others => '-');
|
|
end case;
|
|
end process;
|
|
|
|
P_CodeUnrotating : process (R_Code, R1_SelectRotator)
|
|
begin
|
|
C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
|
|
end process;
|
|
|
|
P_OutMux : process (
|
|
C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P4_Data, S_P5_Data, S_P6_Data, S_P7_Data, S_P8_Data, S_P9_Data, S_P10_Data, S_P11_Data, S_P12_Data, S_P13_Data, S_P14_Data, S_P15_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_P4_Valid, S_P5_Valid, S_P6_Valid, S_P7_Valid, S_P8_Valid, S_P9_Valid, S_P10_Valid, S_P11_Valid, S_P12_Valid, S_P13_Valid, S_P14_Valid, S_P15_Valid, S_Out_Ready)
|
|
begin
|
|
S_Out_Valid <= '0';
|
|
S_P0_Ready <= '0';
|
|
S_P1_Ready <= '0';
|
|
S_P2_Ready <= '0';
|
|
S_P3_Ready <= '0';
|
|
S_P4_Ready <= '0';
|
|
S_P5_Ready <= '0';
|
|
S_P6_Ready <= '0';
|
|
S_P7_Ready <= '0';
|
|
S_P8_Ready <= '0';
|
|
S_P9_Ready <= '0';
|
|
S_P10_Ready <= '0';
|
|
S_P11_Ready <= '0';
|
|
S_P12_Ready <= '0';
|
|
S_P13_Ready <= '0';
|
|
S_P14_Ready <= '0';
|
|
S_P15_Ready <= '0';
|
|
S_Out_Data <= (others => '-');
|
|
S_Out_Address <= C_CodeUnrotated;
|
|
|
|
case C_CodeUnrotated is when "0000" =>
|
|
S_Out_Valid <= S_P0_Valid;
|
|
S_P0_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P0_Data;
|
|
when "0001" =>
|
|
S_Out_Valid <= S_P1_Valid;
|
|
S_P1_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P1_Data;
|
|
when "0010" =>
|
|
S_Out_Valid <= S_P2_Valid;
|
|
S_P2_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P2_Data;
|
|
when "0011" =>
|
|
S_Out_Valid <= S_P3_Valid;
|
|
S_P3_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P3_Data;
|
|
when "0100" =>
|
|
S_Out_Valid <= S_P4_Valid;
|
|
S_P4_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P4_Data;
|
|
when "0101" =>
|
|
S_Out_Valid <= S_P5_Valid;
|
|
S_P5_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P5_Data;
|
|
when "0110" =>
|
|
S_Out_Valid <= S_P6_Valid;
|
|
S_P6_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P6_Data;
|
|
when "0111" =>
|
|
S_Out_Valid <= S_P7_Valid;
|
|
S_P7_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P7_Data;
|
|
when "1000" =>
|
|
S_Out_Valid <= S_P8_Valid;
|
|
S_P8_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P8_Data;
|
|
when "1001" =>
|
|
S_Out_Valid <= S_P9_Valid;
|
|
S_P9_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P9_Data;
|
|
when "1010" =>
|
|
S_Out_Valid <= S_P10_Valid;
|
|
S_P10_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P10_Data;
|
|
when "1011" =>
|
|
S_Out_Valid <= S_P11_Valid;
|
|
S_P11_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P11_Data;
|
|
when "1100" =>
|
|
S_Out_Valid <= S_P12_Valid;
|
|
S_P12_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P12_Data;
|
|
when "1101" =>
|
|
S_Out_Valid <= S_P13_Valid;
|
|
S_P13_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P13_Data;
|
|
when "1110" =>
|
|
S_Out_Valid <= S_P14_Valid;
|
|
S_P14_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P14_Data;
|
|
when "1111" =>
|
|
S_Out_Valid <= S_P15_Valid;
|
|
S_P15_Ready <= S_Out_Ready;
|
|
S_Out_Data <= S_P15_Data;
|
|
when others =>
|
|
S_Out_Address <= (others => '-');
|
|
end case;
|
|
end process;
|
|
|
|
P_SelectRotator : process (I_CLK)
|
|
begin
|
|
if rising_edge(I_CLK) then
|
|
if I_CE = '1' then
|
|
if I_RST = '1' then
|
|
R_SelectRotator <= (others => '0');
|
|
R1_SelectRotator <= (others => '0');
|
|
R_Code <= (others => '0');
|
|
else
|
|
R1_SelectRotator <= R_SelectRotator;
|
|
R_Code <= C_Code;
|
|
if I_Out_Ready = '1' then
|
|
R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process P_SelectRotator;
|
|
|
|
I_OutBufferCtrl : entity work.PipelineController
|
|
generic map(
|
|
G_PipelineStages => G_OutBufferStages
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_CE => I_CE,
|
|
I_RST => I_RST,
|
|
O_Enable => S_OutBufferEnable,
|
|
I_Valid => S_Out_Valid,
|
|
O_Ready => S_Out_Ready,
|
|
O_Valid => O_Out_Valid,
|
|
I_Ready => I_Out_Ready
|
|
);
|
|
|
|
I_OutDataBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_OutBufferStages,
|
|
G_Width => G_DataWidth,
|
|
G_RegisterBalancing => "backward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_OutBufferEnable,
|
|
I_Data => S_Out_Data,
|
|
O_Data => O_Out_Data
|
|
);
|
|
|
|
I_OutAddressBuffer : entity work.PipelineRegister
|
|
generic map(
|
|
G_PipelineStages => G_OutBufferStages,
|
|
G_Width => 4,
|
|
G_RegisterBalancing => "backward"
|
|
)
|
|
port map(
|
|
I_CLK => I_CLK,
|
|
I_Enable => S_OutBufferEnable,
|
|
I_Data => S_Out_Address,
|
|
O_Data => O_Out_Address
|
|
);
|
|
end architecture;
|