Adds YAML-based project configuration loader
Introduces a function to load and parse project configurations from a YAML file, returning a typed object for improved usability and type safety.
This commit is contained in:
41
project.example.yml
Normal file
41
project.example.yml
Normal file
@@ -0,0 +1,41 @@
|
||||
name: VGA_Test
|
||||
topmodule: VGA_Test_Top
|
||||
target_device: xc3s1200e-4-fg320
|
||||
xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
sources:
|
||||
vhdl:
|
||||
- path: src/vga/*.vhd
|
||||
library: work
|
||||
- path: src/common/*.vhd
|
||||
library: work
|
||||
- path: src/VGA_test_top.vhd
|
||||
library: work
|
||||
|
||||
verilog:
|
||||
- path: src/old_modules/*.v
|
||||
library: work
|
||||
|
||||
dependencies:
|
||||
- name: AsyncFIFO
|
||||
git: "https://github.com/0xMax32/Asynchronous-FIFO-AXI-Handshake.git"
|
||||
rev: "main"
|
||||
library: asyncfifo
|
||||
- name: GrayCounter
|
||||
git: "https://github.com/0xMax32/Gray-Counter.git"
|
||||
rev: "v1.0.0"
|
||||
library: graycounter
|
||||
|
||||
testbenches:
|
||||
vhdl:
|
||||
- path: src/tests/*.vhd
|
||||
library: work
|
||||
|
||||
verilog: []
|
||||
|
||||
constraints: constraints/VGA_Test.ucf
|
||||
|
||||
build:
|
||||
build_dir: working
|
||||
report_dir: reports
|
||||
copy_target_dir: output
|
14
src/config.py
Normal file
14
src/config.py
Normal file
@@ -0,0 +1,14 @@
|
||||
from pydantic import BaseModel
|
||||
|
||||
class DirectoryConfig(BaseModel):
|
||||
dependency: str = ".hdlbuild_deps"
|
||||
build: str = ".working"
|
||||
report: str = "reports"
|
||||
copy_target: str = "output"
|
||||
|
||||
DIRECTORIES = DirectoryConfig()
|
||||
|
||||
class GitConfig(BaseModel):
|
||||
timeout: int = 10
|
||||
|
||||
GIT = GitConfig()
|
36
src/models/project.py
Normal file
36
src/models/project.py
Normal file
@@ -0,0 +1,36 @@
|
||||
from pydantic import BaseModel, Field
|
||||
from typing import List, Optional
|
||||
|
||||
class SourceFile(BaseModel):
|
||||
path: str
|
||||
library: str = "work" # Default auf 'work'
|
||||
|
||||
class Dependency(BaseModel):
|
||||
name: str
|
||||
git: str
|
||||
rev: str
|
||||
library: str = "work" # Default auf 'work'
|
||||
|
||||
class Sources(BaseModel):
|
||||
vhdl: List[SourceFile] = Field(default_factory=list)
|
||||
verilog: List[SourceFile] = Field(default_factory=list)
|
||||
|
||||
class Testbenches(BaseModel):
|
||||
vhdl: List[SourceFile] = Field(default_factory=list)
|
||||
verilog: List[SourceFile] = Field(default_factory=list)
|
||||
|
||||
class BuildOptions(BaseModel):
|
||||
build_dir: Optional[str] = "working"
|
||||
report_dir: Optional[str] = "reports"
|
||||
copy_target_dir: Optional[str] = "output"
|
||||
|
||||
class ProjectConfig(BaseModel):
|
||||
name: str
|
||||
topmodule: Optional[str]
|
||||
target_device: str
|
||||
xilinx_path: str
|
||||
sources: Sources
|
||||
testbenches: Optional[Testbenches] = None
|
||||
constraints: Optional[str] = None
|
||||
build: Optional[BuildOptions] = None
|
||||
dependencies: Optional[List[Dependency]] = Field(default_factory=list)
|
16
src/utils/project_loader.py
Normal file
16
src/utils/project_loader.py
Normal file
@@ -0,0 +1,16 @@
|
||||
import yaml
|
||||
from models.project import ProjectConfig
|
||||
|
||||
def load_project_config(path: str = "project.yml") -> ProjectConfig:
|
||||
"""
|
||||
Lädt die Projektkonfiguration aus einer YAML-Datei und gibt ein typisiertes ProjectConfig-Objekt zurück.
|
||||
|
||||
Args:
|
||||
path (str): Pfad zur project.yml Datei (Default: "project.yml")
|
||||
|
||||
Returns:
|
||||
ProjectConfig: Geparstes und typisiertes Projektkonfigurationsobjekt
|
||||
"""
|
||||
with open(path, "r") as file:
|
||||
raw_data = yaml.safe_load(file)
|
||||
return ProjectConfig(**raw_data)
|
Reference in New Issue
Block a user