diff --git a/project.example.yml b/project.example.yml
new file mode 100644
index 0000000..0213934
--- /dev/null
+++ b/project.example.yml
@@ -0,0 +1,41 @@
+name: VGA_Test
+topmodule: VGA_Test_Top
+target_device: xc3s1200e-4-fg320
+xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE
+
+sources:
+  vhdl:
+    - path: src/vga/*.vhd
+      library: work
+    - path: src/common/*.vhd
+      library: work
+    - path: src/VGA_test_top.vhd
+      library: work
+
+  verilog:
+    - path: src/old_modules/*.v
+      library: work
+
+dependencies:
+  - name: AsyncFIFO
+    git: "https://github.com/0xMax32/Asynchronous-FIFO-AXI-Handshake.git"
+    rev: "main"
+    library: asyncfifo
+  - name: GrayCounter
+    git: "https://github.com/0xMax32/Gray-Counter.git"
+    rev: "v1.0.0"
+    library: graycounter
+
+testbenches:
+  vhdl:
+    - path: src/tests/*.vhd
+      library: work
+
+  verilog: []
+
+constraints: constraints/VGA_Test.ucf
+
+build:
+  build_dir: working
+  report_dir: reports
+  copy_target_dir: output
diff --git a/src/config.py b/src/config.py
new file mode 100644
index 0000000..44d7be8
--- /dev/null
+++ b/src/config.py
@@ -0,0 +1,14 @@
+from pydantic import BaseModel
+
+class DirectoryConfig(BaseModel):
+    dependency: str = ".hdlbuild_deps"
+    build: str = ".working"
+    report: str = "reports"
+    copy_target: str = "output"
+
+DIRECTORIES = DirectoryConfig()
+
+class GitConfig(BaseModel):
+    timeout: int = 10
+
+GIT = GitConfig()
\ No newline at end of file
diff --git a/src/models/project.py b/src/models/project.py
new file mode 100644
index 0000000..a2ee897
--- /dev/null
+++ b/src/models/project.py
@@ -0,0 +1,36 @@
+from pydantic import BaseModel, Field
+from typing import List, Optional
+
+class SourceFile(BaseModel):
+    path: str
+    library: str = "work"   # Default auf 'work'
+
+class Dependency(BaseModel):
+    name: str
+    git: str
+    rev: str
+    library: str = "work"   # Default auf 'work'
+
+class Sources(BaseModel):
+    vhdl: List[SourceFile] = Field(default_factory=list)
+    verilog: List[SourceFile] = Field(default_factory=list)
+
+class Testbenches(BaseModel):
+    vhdl: List[SourceFile] = Field(default_factory=list)
+    verilog: List[SourceFile] = Field(default_factory=list)
+
+class BuildOptions(BaseModel):
+    build_dir: Optional[str] = "working"
+    report_dir: Optional[str] = "reports"
+    copy_target_dir: Optional[str] = "output"
+
+class ProjectConfig(BaseModel):
+    name: str
+    topmodule: Optional[str]
+    target_device: str
+    xilinx_path: str
+    sources: Sources
+    testbenches: Optional[Testbenches] = None
+    constraints: Optional[str] = None
+    build: Optional[BuildOptions] = None
+    dependencies: Optional[List[Dependency]] = Field(default_factory=list)
diff --git a/src/utils/project_loader.py b/src/utils/project_loader.py
new file mode 100644
index 0000000..1c6f1e0
--- /dev/null
+++ b/src/utils/project_loader.py
@@ -0,0 +1,16 @@
+import yaml
+from models.project import ProjectConfig
+
+def load_project_config(path: str = "project.yml") -> ProjectConfig:
+    """
+    Lädt die Projektkonfiguration aus einer YAML-Datei und gibt ein typisiertes ProjectConfig-Objekt zurück.
+    
+    Args:
+        path (str): Pfad zur project.yml Datei (Default: "project.yml")
+    
+    Returns:
+        ProjectConfig: Geparstes und typisiertes Projektkonfigurationsobjekt
+    """
+    with open(path, "r") as file:
+        raw_data = yaml.safe_load(file)
+    return ProjectConfig(**raw_data)