Max P
11d446ec3e
**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master) Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
266 lines
8.5 KiB
Makefile
266 lines
8.5 KiB
Makefile
###########################################################################
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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##
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## Makefile github repository: https://github.com/PxaMMaxP/Xilinx-ISE-Makefile
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###########################################################################
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###########################################################################
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# Version
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###########################################################################
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Makefile_Version := 1.1.0
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$(info ISE Makefile Version: $(Makefile_Version))
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###########################################################################
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# Include project configuration
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###########################################################################
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include ../project.cfg
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###########################################################################
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# Default values
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###########################################################################
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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ifndef PROJECT
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$(error PROJECT must be defined)
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endif
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ifndef TARGET_PART
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$(error TARGET_PART must be defined)
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endif
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TOPLEVEL ?= $(PROJECT)
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CONSTRAINTS ?= $(PROJECT).ucf
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BUILD_DIR ?= working
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BITFILE ?= $(BUILD_DIR)/$(PROJECT).bit
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COMMON_OPTS ?= -intstyle xflow
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?= -detail
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?= -v 3 -n 3
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FUSE_OPTS ?= -incremental
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ISIM_OPTS ?= -gui
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ISIM_CMD ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
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PROGRAMMER ?= none
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PROGRAMMER_PRE ?=
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IMPACT_OPTS ?= -batch impact.cmd
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DJTG_EXE ?= djtgcfg
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DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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DJTG_INDEX ?= 0
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DJTG_FLASH_INDEX ?= 1
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= none
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XC3SPROG_OPTS ?=
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###########################################################################
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# Internal variables, platform-specific definitions, and macros
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###########################################################################
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ifeq ($(OS),Windows_NT)
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XILINX := $(shell cygpath -m $(XILINX))
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CYG_XILINX := $(shell cygpath $(XILINX))
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EXE := .exe
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XILINX_PLATFORM ?= nt64
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PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
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else
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EXE :=
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XILINX_PLATFORM ?= lin64
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PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
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endif
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TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
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RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
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cd $(BUILD_DIR) && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
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# isim executables don't work without this
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export XILINX
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# Initialize the libs and paths variables for VHDL and Verilog sources
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VHD_PATHS ?=
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VHD_LIBS ?=
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V_PATHS ?=
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V_LIBS ?=
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# Define a function to process source files
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define process_sources
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$(foreach src,$(1),\
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$(eval lib_and_path=$(subst :, ,$(src))) \
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$(eval libname=$(word 1,$(lib_and_path))) \
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$(eval filepath=$(word 2,$(lib_and_path))) \
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$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
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$(eval $(2) += $(libname)) \
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$(eval $(3) += ../$(filepath)) \
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)
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endef
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# Run the function for VHDL sources
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$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
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# Run the function for Verilog sources
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$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
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## Tests
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# Initialize the libs and paths variables for VHDL and Verilog testbenches
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VHD_TEST_PATHS ?=
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VHD_TEST_LIBS ?=
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V_TEST_PATHS ?=
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V_TEST_LIBS ?=
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# Run the function for VHDL tests
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$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
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# Run the function for Verilog tests
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$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
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# Get the test names..
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TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
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TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
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###########################################################################
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# Default build
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###########################################################################
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default: $(BITFILE)
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clean:
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rm -rf $(BUILD_DIR)
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$(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
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@echo "Updating $@"
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@mkdir -p $(BUILD_DIR)
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@rm -f $@
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@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
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@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
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$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
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@cp $(BUILD_DIR)/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
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@echo "Updating $@"
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@mkdir -p $(BUILD_DIR)
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@rm -f $@
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@echo "run" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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> $(BUILD_DIR)/$(PROJECT).scr
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$(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj $(BUILD_DIR)/$(PROJECT).scr
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@mkdir -p $(BUILD_DIR)
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$(call RUN,xst) $(COMMON_OPTS) \
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-ifn $(PROJECT).scr
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$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
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-p $(TARGET_PART) -uc ../../$(CONSTRAINTS) \
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$(PROJECT).ngc $(PROJECT).ngd
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$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
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-p $(TARGET_PART) \
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-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
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$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
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-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
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$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo "\e[1;32m============ OK ============\e[m\n\n"
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@echo "\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).srp\e[m\n"
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@echo "\e[1;97m======= Map Summary Report =======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).map.mrp\e[m\n"
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@echo "\e[1;97m======= PAR Summary Report =======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).par\e[m\n"
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@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
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###########################################################################
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# Testing (work in progress)
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###########################################################################
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trace: ../project.cfg $(BITFILE)
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$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
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$(PROJECT).ncd $(PROJECT).pcf
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@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m===== Timing Summary Report ======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
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test: buildtest runtest
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runtest: ${TEST_NAMES}
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${TEST_NAMES}:
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@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > build/isim_$@.cmd
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@echo "$(ISIM_CMD)" >> build/isim_$@.cmd
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cd build ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
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buildtest: ${TEST_EXES}
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$(BUILD_DIR)/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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###########################################################################
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# Programming
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###########################################################################
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ifeq ($(PROGRAMMER), impact)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
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endif
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ifeq ($(PROGRAMMER), digilent)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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###########################################################################
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# Flash
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###########################################################################
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ifeq ($(PROGRAMMER), digilent)
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flash: $(BITFILE)
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$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
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endif
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###########################################################################
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