Max P
11d446ec3e
**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master) Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
8.5 KiB
8.5 KiB