Files
Xilinx-ISE-Build/tests/test_generate_scr.py
MaxP 2fce367686 Add project configuration and build tools
- Introduced new scripts for project generation and synthesis (dodo.py, generate_prj.py, generate_scr.py, run_xst.py).
- Implemented configuration parsing for VHDL sources and project settings (config.py).
- Added default configuration values (defaults.py).
- Updated .gitignore to include additional file types.
- Created test cases for project generation and configuration parsing (test_generate_prj.py, test_generate_scr.py, test_project_cfg.py).
2025-04-20 11:32:37 +00:00

45 lines
1.2 KiB
Python

from pathlib import Path
from tasks.generate_scr import generate_scr
def write_file(path: Path, content: str):
path.write_text(content.strip(), encoding="utf-8")
def test_generate_scr_basic(tmp_path):
cfg_path = tmp_path / "project.cfg"
scr_path = tmp_path / "working" / "MyProject.scr"
write_file(cfg_path, """
PROJECT = MyProject
TARGET_PART = xc3s50-4-pq208
XILINX = /some/path
""")
generate_scr(scr_path, cfg_path)
content = scr_path.read_text()
assert "-ifn MyProject.prj" in content
assert "-ofn MyProject.ngc" in content
assert "-top MyProject" in content
assert "-p xc3s50-4-pq208" in content
def test_generate_scr_with_top_and_opts(tmp_path):
cfg_path = tmp_path / "project.cfg"
scr_path = tmp_path / "working" / "MyProject.scr"
write_file(cfg_path, """
PROJECT = MyProject
TARGET_PART = xc3s200-5-ft256
TOPLEVEL = TopModule
XST_OPTS = -opt_mode Speed -opt_level 2
XILINX = /some/path
""")
generate_scr(scr_path, cfg_path)
content = scr_path.read_text()
assert "-top TopModule" in content
assert "-opt_mode Speed -opt_level 2" in content