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feature/ad
Author | SHA1 | Date | |
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033dede087 | |||
a8ed470e7d | |||
139e4718fa | |||
11d446ec3e |
54
Makefile
54
Makefile
@@ -12,7 +12,7 @@
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# Version
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###########################################################################
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Makefile_Version := 1.0.3
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Makefile_Version := 1.1.3
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$(info ISE Makefile Version: $(Makefile_Version))
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###########################################################################
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@@ -50,6 +50,9 @@ PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?= -v 3 -n 3
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FUSE_OPTS ?= -incremental
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ISIM_OPTS ?= -gui
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ISIM_CMD ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
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PROGRAMMER ?= none
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PROGRAMMER_PRE ?=
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@@ -114,6 +117,24 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
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# Run the function for Verilog sources
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$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
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## Tests
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# Initialize the libs and paths variables for VHDL and Verilog testbenches
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VHD_TEST_PATHS ?=
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VHD_TEST_LIBS ?=
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V_TEST_PATHS ?=
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V_TEST_LIBS ?=
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# Run the function for VHDL tests
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$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
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# Run the function for Verilog tests
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$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
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# Get the test names..
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TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
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TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
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###########################################################################
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# Default build
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###########################################################################
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@@ -133,8 +154,8 @@ $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
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$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
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@cp $(BUILD_DIR)/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
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@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
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@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
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@@ -176,7 +197,9 @@ $(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR
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@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
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copy: $(BITFILE)
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@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
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@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
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###########################################################################
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# Testing (work in progress)
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@@ -189,24 +212,23 @@ trace: ../project.cfg $(BITFILE)
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@echo "\e[1;97m===== Timing Summary Report ======\e[m"
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@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
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test: $(TEST_EXES)
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test: buildtest runtest
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$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
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runtest: ${TEST_NAMES}
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${TEST_NAMES}:
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@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
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@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
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cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
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buildtest: ${TEST_EXES}
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$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
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@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
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cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
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isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
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@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
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cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
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###########################################################################
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# Programming
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