Adjusts delay in monitoring script and adds clock frequency calculator

Increases the delay in the monitoring script from 1 second to 3 seconds to reduce resource strain during rapid file changes.

Introduces a new Python script for calculating optimal clock frequency settings based on input and target frequencies.

.gitignore

@@ -1 +1,2 @@
-working/
+working/
+reports/

Makefile

@@ -12,7 +12,7 @@
 # Version
 ###########################################################################
 
-Makefile_Version := 1.0.3
+Makefile_Version := 1.1.5
 $(info ISE Makefile Version: $(Makefile_Version))
 
 ###########################################################################
@@ -40,6 +40,7 @@ endif
 TOPLEVEL         ?= $(PROJECT)
 CONSTRAINTS      ?= $(PROJECT).ucf
 BUILD_DIR        ?= working
+REPORT_DIR       ?= reports
 BITFILE          ?= $(BUILD_DIR)/$(PROJECT).bit
  
 COMMON_OPTS      ?= -intstyle xflow
@@ -50,6 +51,9 @@ PAR_OPTS         ?=
 BITGEN_OPTS      ?=
 TRACE_OPTS       ?= -v 3 -n 3
 FUSE_OPTS        ?= -incremental
+
+ISIM_OPTS		 ?= -gui
+ISIM_CMD		 ?= 
  
 PROGRAMMER       ?= none
 PROGRAMMER_PRE   ?=
@@ -114,6 +118,24 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
 # Run the function for Verilog sources
 $(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
 
+## Tests
+
+# Initialize the libs and paths variables for VHDL and Verilog testbenches
+VHD_TEST_PATHS ?=
+VHD_TEST_LIBS  ?=
+V_TEST_PATHS   ?=
+V_TEST_LIBS    ?=
+
+# Run the function for VHDL tests
+$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
+# Run the function for Verilog tests
+$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
+
+# Get the test names..
+TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
+TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
+TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
+
 ###########################################################################
 # Default build
 ###########################################################################
@@ -122,10 +144,12 @@ default: $(BITFILE)
 
 clean:
 	rm -rf $(BUILD_DIR)
+	rm -rf $(REPORT_DIR)
 
 $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
 	@echo "Updating $@"
 	@mkdir -p $(BUILD_DIR)
+	@mkdir -p $(REPORT_DIR)
 	@rm -f $@
 	@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
 	@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
@@ -133,8 +157,8 @@ $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
 
 $(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
 	@cp $(BUILD_DIR)/$(PROJECT).prj $@
-	@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
-	@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
+	@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
+	@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
 	@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
 
 $(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
@@ -153,30 +177,37 @@ $(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
 
 $(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj $(BUILD_DIR)/$(PROJECT).scr
 	@mkdir -p $(BUILD_DIR)
+	@mkdir -p $(REPORT_DIR)
 	$(call RUN,xst) $(COMMON_OPTS) \
 	    -ifn $(PROJECT).scr
+	@cp ./$(BUILD_DIR)/$(PROJECT).srp $(REPORT_DIR)/$(PROJECT).SynthesisReport
 	$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
 	    -p $(TARGET_PART) -uc ../../$(CONSTRAINTS) \
 	    $(PROJECT).ngc $(PROJECT).ngd
 	$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
 	    -p $(TARGET_PART) \
 	    -w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
+	@cp ./$(BUILD_DIR)/$(PROJECT).map.mrp $(REPORT_DIR)/$(PROJECT).MapReport
 	$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
 	    -w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
+	@cp ./$(BUILD_DIR)/$(PROJECT).par $(REPORT_DIR)/$(PROJECT).PlaceRouteReport
 	$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
 	    -w $(PROJECT).ncd $(PROJECT).bit
 	@echo "\e[1;32m============ OK ============\e[m\n\n"
 	@echo "\e[1;33m============ Reports.. ===========\e[m\n"
 	@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
-	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).srp\e[m\n"
+	@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).SynthesisReport\e[m\n"
 	@echo "\e[1;97m======= Map Summary Report =======\e[m"
-	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).map.mrp\e[m\n"
+	@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).MapReport\e[m\n"
 	@echo "\e[1;97m======= PAR Summary Report =======\e[m"
-	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).par\e[m\n"
+	@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PlaceRouteReport\e[m\n"
 	@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
-	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
-	
+	@cp ./$(BUILD_DIR)/$(PROJECT)_pad.txt $(REPORT_DIR)/$(PROJECT).PinoutReport
+	@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PinoutReport\e[m\n"
 
+copy: $(BITFILE)
+	@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
+	@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
 
 ###########################################################################
 # Testing (work in progress)
@@ -187,26 +218,26 @@ trace: ../project.cfg $(BITFILE)
 	    $(PROJECT).ncd $(PROJECT).pcf
 	@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
 	@echo "\e[1;97m===== Timing Summary Report ======\e[m"
-	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
+	@cp ./$(BUILD_DIR)/$(PROJECT).twr $(REPORT_DIR)/$(PROJECT).TimingReport
+	@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).TimingReport\e[m\n"
 
-test: $(TEST_EXES)
+test: buildtest runtest
 
-$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
+runtest: ${TEST_NAMES}
+
+${TEST_NAMES}:
+	@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
+	@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
+	cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
+
+buildtest: ${TEST_EXES}
+
+$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
 	$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
 	    -prj $(PROJECT)_sim.prj \
 	    -o isim_$*$(EXE) \
 	    work.$* work.glbl
 
-isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
-	@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
-	@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
-	cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
-
-isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
-	@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
-	@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
-	cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
-
 
 ###########################################################################
 # Programming

autoflash.sh

@@ -0,0 +1,83 @@
+#!/bin/bash
+
+# 🧠 Show help message
+function show_help() {
+    echo "Usage: $0 [-d device] [-i index] TopModuleName"
+    echo
+    echo "Arguments:"
+    echo "  -d <device>   Name of the USB device (e.g., DOnbUsb), optional (default: DOnbUsb)"
+    echo "  -i <index>    Interface index, optional (default: 0)"
+    echo "  TopModule     Name of the top module (e.g., VGATimingGenerator)"
+    exit 1
+}
+
+# 🔧 Default values
+DEVICE="DOnbUsb"
+INDEX=0
+
+# 🧩 Parse arguments
+while [[ "$1" =~ ^- ]]; do
+    case "$1" in
+        -d)
+            shift
+            DEVICE="$1"
+            ;;
+        -i)
+            shift
+            INDEX="$1"
+            ;;
+        -h|--help)
+            show_help
+            ;;
+        *)
+            echo "❌ Unknown option: $1"
+            show_help
+            ;;
+    esac
+    shift
+done
+
+# 📛 Get top module name
+TOPMODULE="$1"
+
+if [ -z "$TOPMODULE" ]; then
+    echo "❌ Error: No top module specified."
+    show_help
+fi
+
+# 📂 Path to bitstream file
+BITFILE="working/${TOPMODULE}.bit"
+
+# 📡 Flashing function
+function flash_bitstream() {
+    echo "⚡ Flashing bitstream to device $DEVICE, index $INDEX..."
+    yes Y | djtgcfg prog -d "$DEVICE" -i "$INDEX" -f "$BITFILE"
+}
+
+# 🧹 Cleanup on Ctrl+C
+function cleanup() {
+    echo
+    echo "👋 Terminated. Auto-flashing is no longer active."
+    exit 0
+}
+trap cleanup SIGINT
+
+# 🔍 Initial check
+if [ -f "$BITFILE" ]; then
+    echo "📦 Bitstream file $BITFILE found. Starting initial flash..."
+    flash_bitstream
+    echo "✅ Initial flash completed. Waiting for changes..."
+else
+    echo "⚠️  Bitstream file $BITFILE does not exist yet. Waiting for initial creation..."
+fi
+
+echo "👂 Monitoring $BITFILE for changes... (Press Ctrl+C to exit)"
+
+# ♻️ Infinite watch loop
+while true; do
+    inotifywait -e close_write "$BITFILE" >/dev/null 2>&1
+    echo "🌀 Change detected. Waiting 3 second..."
+    sleep 3
+    flash_bitstream
+    echo "✅ Done. Waiting for next change..."
+done

clkfx.py

@@ -0,0 +1,29 @@
+def find_best_clkfx(input_freq, target_freq):
+    best_m = 0
+    best_d = 0
+    best_error = float('inf')
+    best_output = 0
+
+    for m in range(2, 33):  # CLKFX_MULTIPLY 2..32
+        for d in range(1, 33):  # CLKFX_DIVIDE 1..32
+            output_freq = input_freq * m / d
+            error = abs(output_freq - target_freq)
+
+            if error < best_error:
+                best_error = error
+                best_m = m
+                best_d = d
+                best_output = output_freq
+
+    relative_error = (best_error / target_freq) * 100
+
+    print(f"Beste Werte:")
+    print(f"  CLKFX_MULTIPLY => {best_m}")
+    print(f"  CLKFX_DIVIDE   => {best_d}")
+    print(f"Erzeugte Frequenz: {best_output:.6f} MHz")
+    print(f"Abweichung: {best_error:.6f} MHz ({relative_error:.3f}%)")
+
+if __name__ == "__main__":
+    input_freq = float(input("Eingangsfrequenz (MHz): "))
+    target_freq = float(input("Ziel-Frequenz (MHz): "))
+    find_best_clkfx(input_freq, target_freq)

project.cfg.sample

@@ -0,0 +1,110 @@
+## Main settings.. ##
+
+# Project name
+# @remark The name of the project is used as default name for the top module and the ucf file
+PROJECT = 
+
+# Target device
+# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
+TARGET_PART = 
+
+# Path to the Xilinx ISE installation
+XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
+
+# Optional the name of the top module (default is the project name)
+# TOPLEVEL = 
+
+# Optional the path/name of the ucf file (default is the project name)
+# CONSTRAINTS = 
+
+# Optional a target to copy the bit file to (make copy)
+# COPY_TARGET_DIR = 
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Source files settings.. ##
+# The source files to be compiled
+# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
+# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
+
+
+## Test files settings.. ##
+# The testbench files to be compiled
+# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
+# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
+
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## ISE executable settings.. ##
+
+# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
+# COMMON_OPTS = 
+
+# Options for the XST synthesizer
+# @example -register_balancing (yes|no)
+# @example -opt_mode (speed|area)
+# @example -opt_level (1|2)
+XST_OPTS = 
+
+# Options for the NGDBuild tool
+# NGDBUILD_OPTS =
+
+# Options for the MAP tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -cm speed (speed optimization)
+# @example -ol high
+# @example -detail
+# @example -timing
+MAP_OPTS = 
+
+# Options for the PAR tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -ol high
+PAR_OPTS = 
+
+# Options for the BitGen tool
+# @example -g Compress (compress bitstream)
+# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
+# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
+BITGEN_OPTS = -g StartupClk:JtagClk
+
+# Options for the Trace tool
+# TRACE_OPTS = 
+
+# Options for the Fuse tool
+# FUSE_OPTS = 
+
+# Options for the ISim simulator
+# @example -gui (start the simulator in GUI mode)
+# ISIM_OPTS =
+
+# Options for the ISim batch file
+# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
+# ISIM_CMD =
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Programmer settings.. ##
+
+# The programmer to use
+# @example impact | digilent | xc3sprog
+# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
+PROGRAMMER = 
+
+## Digilent JTAG cable settings
+
+# @remark Use the `djtgcfg enum` command to list all available devices
+# DJTG_DEVICE = DOnbUsb
+
+# The index of the JTAG device for the `prog` target
+# DJTG_INDEX = 0
+
+# The index of the flash device for the `flash` target
+# DJTG_FLASH_INDEX = 1
+
+## ## ## ## ## ## ## ##
+# ---------------------