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merge into: maxp:main
Branches Tags
maxp:main maxp:dodo maxp:feature/transpiling maxp:feature/add-testbench-simulation-support
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pull from: maxp:feature/transpiling
Branches Tags
maxp:main maxp:dodo maxp:feature/transpiling maxp:feature/add-testbench-simulation-support

5 Commits
main ... feature/tr

Author SHA1 Message Date
Max P
6b3dd934cd Add .locale/ to .gitignore 
- Ignored `.locale/` directory to `.gitignore` file
- Maintained existing ignore of `working/` directory
 2024-08-29 17:30:14 +02:00
Max P
e3c98ee2ac Add transpiling support 
- Bumped Makefile version to `1.2.0-alpha`
- Introduced `TRANSPILING_DIR` variable
- Added `transpile` target to handle VHDL transpiling
- Updated `BITFILE` dependencies to include `transpile` target
- Included conditional transpiling logic with `ghdl` commands
 2024-08-29 17:26:57 +02:00
Max P
a8ed470e7d Updated Makefile for consistent build output paths and dynamic project references 
Enhanced the Makefile to use a centralized `BUILD_DIR` variable for executable paths, increasing consistency across the build process. Adjusted the project reference generation to dynamically pair test files with their respective libraries, ensuring a more accurate and maintainable build configuration. This change streamlines the build workflow and mitigates potential errors due to path mismatches or hard-coded library links.
 2024-03-10 16:53:24 +01:00
Max P
139e4718fa Update Makefile to version 1.1.1 2024-03-10 16:11:26 +01:00
Max P
11d446ec3e Update Makefile for ISIM test enhancements and version bump 
**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)

Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
 2024-03-10 16:09:21 +01:00
2 changed files with 59 additions and 18 deletions
Expand all files Collapse all files

3
.gitignore vendored
View File

@@ -1 +1,2 @@
working/
working/
.locale/

74
Makefile
View File

@@ -12,7 +12,7 @@
# Version
###########################################################################
Makefile_Version := 1.0.3
Makefile_Version := 1.2.0-alpha
$(info ISE Makefile Version: $(Makefile_Version))
###########################################################################
@@ -40,8 +40,9 @@ endif
TOPLEVEL ?= $(PROJECT)
CONSTRAINTS ?= $(PROJECT).ucf
BUILD_DIR ?= working
TRANSPILING_DIR ?= transpiling
BITFILE ?= $(BUILD_DIR)/$(PROJECT).bit
COMMON_OPTS ?= -intstyle xflow
XST_OPTS ?=
NGDBUILD_OPTS ?=
@@ -50,6 +51,9 @@ PAR_OPTS ?=
BITGEN_OPTS ?=
TRACE_OPTS ?= -v 3 -n 3
FUSE_OPTS ?= -incremental
ISIM_OPTS ?= -gui
ISIM_CMD ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
PROGRAMMER ?= none
PROGRAMMER_PRE ?=
@@ -114,6 +118,24 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
# Run the function for Verilog sources
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
## Tests
# Initialize the libs and paths variables for VHDL and Verilog testbenches
VHD_TEST_PATHS ?=
VHD_TEST_LIBS ?=
V_TEST_PATHS ?=
V_TEST_LIBS ?=
# Run the function for VHDL tests
$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
# Run the function for Verilog tests
$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
# Get the test names..
TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
###########################################################################
# Default build
###########################################################################
@@ -133,8 +155,8 @@ $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
@cp $(BUILD_DIR)/$(PROJECT).prj $@
@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
@@ -151,7 +173,7 @@ $(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
"-p $(TARGET_PART)" \
> $(BUILD_DIR)/$(PROJECT).scr
$(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj $(BUILD_DIR)/$(PROJECT).scr
$(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj transpile $(BUILD_DIR)/$(PROJECT).scr
@mkdir -p $(BUILD_DIR)
$(call RUN,xst) $(COMMON_OPTS) \
-ifn $(PROJECT).scr
@@ -176,6 +198,25 @@ $(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR
@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
###########################################################################
# Transpiling (work in progress)
###########################################################################
transpile:
ifeq ($(TRANSPILING),true)
@echo "Transpiling is enabled"
@mkdir -p ./$(BUILD_DIR)/$(TRANSPILING_DIR)/dist
@for idx in $(shell seq 1 $(words $(VHD_PATHS))); do \
vhdl_path=$$(echo $(VHD_PATHS) | cut -d ' ' -f $$idx); \
vhdl_lib=$$(echo $(VHD_LIBS) | cut -d ' ' -f $$idx); \
echo "Analyzing $$vhdl_path for library $$vhdl_lib..."; \
ghdl -a --std=08 --workdir=./$(BUILD_DIR)/$(TRANSPILING_DIR)/dist "./$$vhdl_path"; \
done
ghdl --synth --std=08 --workdir=./$(BUILD_DIR)/$(TRANSPILING_DIR)/dist --out=raw-vhdl $(TOPLEVEL) > ./$(BUILD_DIR)/$(TRANSPILING_DIR)/$(TOPLEVEL).vhd
@echo "vhdl work \"$(TRANSPILING_DIR)/$(TOPLEVEL).vhd\"" > $(BUILD_DIR)/$(PROJECT).prj
else
@echo "Transpiling is disabled"
endif
###########################################################################
@@ -189,24 +230,23 @@ trace: ../project.cfg $(BITFILE)
@echo "\e[1;97m===== Timing Summary Report ======\e[m"
@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
test: $(TEST_EXES)
test: buildtest runtest
$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
runtest: ${TEST_NAMES}
${TEST_NAMES}:
@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
buildtest: ${TEST_EXES}
$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
-prj $(PROJECT)_sim.prj \
-o isim_$*$(EXE) \
work.$* work.glbl
isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
###########################################################################
# Programming