Major rework - separate config from Makefile; add README
This commit is contained in:
Dusk
92
Makefile
92
Makefile
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## Uncomment these lines and set them appropriately.
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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#PROJECT = <project name>
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include project.cfg
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#TOPLEVEL = <top-level module name>
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#CONSTRAINTS = <constraints file name>.ucf
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#TARGET_PART = <part name, e.g. xc6slx9-2-tqg144>
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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## Where are the Xilinx tools installed?
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ifndef PROJECT
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$(error PROJECT must be defined)
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endif
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#(Linux) XILINX = /opt/xilinx/14.7/ISE_DS/ISE/bin/lin
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ifndef TARGET_PART
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#(Windows) XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
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$(error TARGET_PART must be defined)
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endif
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TOPLEVEL ?= $(PROJECT)
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CONSTRAINTS ?= $(PROJECT).ucf
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BITFILE ?= build/$(PROJECT).bit
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## What are your HDL source files? Repeat this line for each file.
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COMMON_OPTS ?= -intstyle xflow
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?=
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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#VSOURCE += example.v
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PROGRAMMER ?= none
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IMPACT_OPTS ?= -batch impact.cmd
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## These settings are probably fine for most projects.
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DJTG_EXE ?= djtgcfg
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DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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COMMON_OPTS = -intstyle xflow
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DJTG_INDEX ?= 0
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NGDBUILD_OPTS =
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MAP_OPTS = -mt 2
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PAR_OPTS = -mt 2
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TRCE_OPTS = -e
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BITGEN_OPTS = -g Compress
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= -c none
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XC3SPROG_OPTS ?=
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###########################################################################
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###########################################################################
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BITFILE = build/$(PROJECT).bit
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RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
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RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
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cd build && $(XILINX)/$(1)
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cd build && $(XILINX)/$(1)
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@@ -39,13 +51,14 @@ default: $(BITFILE)
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clean:
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clean:
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rm -rf build
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rm -rf build
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build/$(PROJECT).prj: Makefile
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build/$(PROJECT).prj: project.cfg
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@echo "Updating $@"
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@echo "Updating $@"
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@mkdir -p build
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@mkdir -p build
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@rm -f $@
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@rm -f $@
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@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
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build/$(PROJECT).scr: Makefile
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build/$(PROJECT).scr: project.cfg
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@echo "Updating $@"
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@echo "Updating $@"
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@mkdir -p build
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@mkdir -p build
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@rm -f $@
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@rm -f $@
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@@ -53,12 +66,13 @@ build/$(PROJECT).scr: Makefile
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"-ifn $(PROJECT).prj" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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"-p $(TARGET_PART)" \
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> build/$(PROJECT).scr
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> build/$(PROJECT).scr
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$(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
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$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
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@mkdir -p build
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@mkdir -p build
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$(call RUN,xst) $(COMMON_OPTS) \
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$(call RUN,xst) $(COMMON_OPTS) \
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-ifn $(PROJECT).scr
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-ifn $(PROJECT).scr
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@@ -74,16 +88,24 @@ $(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJ
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-w $(PROJECT).ncd $(PROJECT).bit
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo -ne "\e[1;32m======== OK ========\e[m\n"
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@echo -ne "\e[1;32m======== OK ========\e[m\n"
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## You'll need to write an impact.cmd if you want to use this part.
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ifeq ($(PROGRAMMER), impact)
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## A simple one looks like:
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##
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## setMode -bscan
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## setCable -p auto
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## addDevice -p 1 -file build/projectname.bit
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## program -p 1
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## quit
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##
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## You may need to change this rule to something else entirely if your board
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## doesn't support Impact.
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prog: $(BITFILE)
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prog: $(BITFILE)
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$(XILINX)/impact -batch impact.cmd
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$(XILINX)/impact -batch $(IMPACT_OPTS)
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endif
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ifeq ($(PROGRAMMER), digilent)
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prog: $(BITFILE)
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$(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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$(XC3SPROG_EXE) $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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# vim: set filetype=make: #
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170
README.md
Normal file
170
README.md
Normal file
@@ -0,0 +1,170 @@
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Xilinx ISE Makefile
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===================
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Tired of clicking around in Xilinx ISE? Run your builds from the command line!
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Requirements
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------------
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* Xilinx ISE, ideally 14.7 (the final version)
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* GNU (or compatible?) Make
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Install this through Cygwin on Windows.
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Creating a project
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------------------
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To start building a project, you will need to create a file `project.cfg` in
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the top level of your project. This file is a text file sourced by Make, so
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it consists of `KEY = value` pairs. It must define at least the following keys:
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* `PROJECT`
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The name of the project, used as a name for certain intermediate files, and
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as the default name for the top-level module and constraints file.
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* `TARGET_PART`
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The full part-speed-package identifier for the Xilinx part to be targeted,
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e.g. `xc6slx9-2-tqg144`.
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* `XILINX`
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The path to the appropriate binaries directory of the target Xilinx ISE
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install, e.g.
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`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64`
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or
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`/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64`
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for typical installs.
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* `VSOURCE` and/or `VHDSOURCE`
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The space-separated names of all Verilog and/or VHDL source files to be
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used in the project.
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You can define these on multiple lines using `+=`, e.g.
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VSOURCE += foo.v
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VSOURCE += bar.v
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A simple `project.cfg` may thus resemble:
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PROJECT = example
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TARGET_PART = xc6slx9-2-cpg196
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XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
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VSOURCE = example.v
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A number of other keys can be set in the project configuration, including:
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* `TOPLEVEL`
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The name of the top-level module to be used in the project.
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(Defaults to `$PROJECT`.)
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* `CONSTRAINTS`
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The name of the constraints file (`.ucf`) to be used for the project.
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(Defaults to `$PROJECT.ucf`.)
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* `COMMON_OPTS`
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Extra command-line options to be passed to all ISE executables. Defaults to
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`-intstyle xflow`.
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* `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`
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Extra command-line options to be passed to the corresponding ISE tools. All
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default to empty.
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Note that `XST_OPTS` will not appear on the command line during
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compilation, as the XST options are embedded in a script file.
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`MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading,
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which may speed up compilation of large designs.
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`BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression.
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* `PROGRAMMER`
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The name of the programmer to be used for `make prog`. Currently supported
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values are:
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* `impact`
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Uses Xilinx iMPACT for programming, using a batch file named
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`impact.cmd` by default. The iMPACT command line may be overridden by
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setting `IMPACT_OPTS`.
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A typical batch file may resemble:
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setMode -bscan
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setCable -p auto
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addDevice -p 1 -file build/projectname.bit
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program -p 1
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quit
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* `djtg`
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Uses the Digilent JTAG utility for programming, which must be installed
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separately. The name of the board must be set as `DJTG_DEVICE`; the
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path to the djtgcfg executable can be set as `DJTG_EXE`, and the index
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of the device can be set as `DJTG_INDEX`.
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* `xc3sprog`
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Uses the xc3sprog utility for programming, which must also be installed
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separately. The cable name must be set as `XC3SPROG_CABLE`; additional
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options can be set as `XC3SPROG_OPTS`.
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Targets
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-------
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The Xilinx ISE Makefile implements the following targets:
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* `make default` (or just `make`)
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Builds the bitstream.
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* `make clean`
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Removes the build directory.
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* `make prog`
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Writes the bitstream to a target device. Requires some additional
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configuration; see below for details.
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Unimplemented features
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----------------------
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The following features are not currently implemented. (Pull requests are
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encouraged!)
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* Building and/or running testbenches
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* Generation of SPI or other unusual programming files
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* CPLD synthesis
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* Synthesis tools other than XST
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* Display and/or handling of warnings and errors from `build/_xmsgs`
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* Anything else (open an issue?)
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License
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-------
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To the extent possible under law, the author(s) have dedicated all copyright
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and related and neighboring rights to this software to the public domain
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worldwide. This software is distributed without any warranty.
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See LICENSE.md for details.
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Reference in New Issue
Block a user