This website requires JavaScript.
Explore
Help
Sign In
HDL
/
VGA
Watch
1
Star
0
Fork
0
You've already forked VGA
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
14
Commits
1
Branch
0
Tags
1011989322593f1e06590b0a38ad251767fc7031
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Max P
1011989322
Adds project configuration file for VGA design with Xilinx ISE settings
2025-04-27 19:27:56 +00:00
.devcontainer
Adds initial devcontainer configuration for Xilinx ISE 14.7
2025-04-27 19:27:50 +00:00
src
Refactors VGA timing and mode handling
2025-04-26 10:26:52 +00:00
tests
Refactors VGA timing and mode handling
2025-04-26 10:26:52 +00:00
.gitignore
Updates .gitignore to include additional build and output directories
2025-04-27 19:27:01 +00:00
project.cfg
Refactors VGA timing and mode handling
2025-04-26 10:26:52 +00:00
project.yml
Adds project configuration file for VGA design with Xilinx ISE settings
2025-04-27 19:27:56 +00:00
Description
No description provided
60
KiB
Languages
VHDL
100%
