Commit Graph

2 Commits

Author SHA1 Message Date
50f36afcf4 Adds VGA controller and testbench enhancements
Introduces a new VGA module for pixel rendering and sync signal generation. Implements an XY position generator for coordinate management. Updates testbench with color cycling logic and additional color constants. Adjusts timing generator logic for improved sync signal handling and accuracy. Modifies UCF constraints for compatibility with LVTTL standard.

Improves modularity and flexibility of the VGA system.
2025-04-25 15:59:37 +00:00
860108547f Add project configuration and VHDL language server settings 2025-03-27 15:59:53 +00:00