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Refines VHDL formatting and counter logic

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Aligns signal and port declarations for improved readability.
Adjusts horizontal and vertical counter bit-width calculations for accuracy.
Splits conditional statements across multiple lines for better clarity.

No functional changes introduced.
This commit is contained in:
0xMax42
2025-04-16 17:29:41 +00:00
parent cd6524c62e
commit ff7782fd91
2 changed files with 26 additions and 40 deletions
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10
src/VGATimingGenerator.vhd
View File

@@ -56,9 +56,9 @@ end entity VGATimingGenerator;
architecture RTL of VGATimingGenerator is
--@ Horizontal Counter; max value = G_HTotal
signal R_HorizontalCounter : unsigned(integer(ceil(log2(real(G_HTotal)))) downto 0) := (others => '0');
signal R_HorizontalCounter : unsigned(integer(ceil(log2(real(G_HTotal)))) - 1 downto 0) := (others => '0');
--@ Vertical Counter; max value = G_VTotal
signal R_VerticalCounter : unsigned(integer(ceil(log2(real(G_VTotal)))) downto 0) := (others => '0');
signal R_VerticalCounter : unsigned(integer(ceil(log2(real(G_VTotal)))) - 1 downto 0) := (others => '0');
--@ Counter Enable signal for Vertical Counter
signal C_VerticalCE : std_logic := '0';
@@ -112,7 +112,8 @@ begin
--@ Flag generator for horizontal visible area.
P_HorizontalVisible : process (R_HorizontalCounter)
begin
if R_HorizontalCounter >= G_HSync + G_HBack and R_HorizontalCounter <= G_HTotal - G_HFront - 1 then
if R_HorizontalCounter >= G_HSync + G_HBack and
R_HorizontalCounter <= G_HTotal - G_HFront - 1 then
C_HorizontalVisible <= '1';
else
C_HorizontalVisible <= '0';
@@ -166,7 +167,8 @@ begin
--@ Flag generator for vertical visible area.
P_VerticalVisible : process (R_VerticalCounter)
begin
if R_VerticalCounter >= G_VSync + G_VBack and R_VerticalCounter <= G_VTotal - G_VFront - 1 then
if R_VerticalCounter >= G_VSync + G_VBack and
R_VerticalCounter <= G_VTotal - G_VFront - 1 then
C_VerticalVisible <= '1';
else
C_VerticalVisible <= '0';

16
vhdl_ls.toml
View File

@@ -1,16 +0,0 @@
[libraries]
defaultlib.files = [
'tests/*.vhd',
'src/*.vhd',
'src/*/*.vhd',
]
# Libraries can be marked as third-party to disable some analysis warnings, such as unused declarations
UNISIM.files = [
'/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/unisims/unisim_VCOMP.vhd',
]
UNISIM.is_third_party = true
[lint]
unused = 'error' # Upgrade the 'unused' diagnostic to the 'error' severity
unnecessary_work_library = false # Disable linting for the 'library work;' statement