Refactors VGA timing and mode handling

Renames and restructures VGA timing generator for clarity and modularity.
Introduces VGA modes package for centralized resolution and timing configuration.
Updates related testbenches and constraints to align with new structure.
Improves maintainability and flexibility for future VGA mode additions.

tests/VGATimingGenerator_test_tb.vhd

@@ -17,17 +17,21 @@ architecture bench of VGATimingGenerator_test_tb is
   signal O_Red        : std_logic_vector(2 downto 0);
   signal O_Green      : std_logic_vector(2 downto 0);
   signal O_Blue       : std_logic_vector(1 downto 0);
+  signal O_Pixel      : std_logic_vector(7 downto 0);
 begin
 
-  VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
+  VGATimingGenerator_test_inst : entity work.VGA_test
     port map (
       I_CLK       => I_CLK,
       O_VGA_HSync => O_HSync,
       O_VGA_VSync => O_VSync,
-      O_Red       => O_Red,
-      O_Green     => O_Green,
-      O_Blue      => O_Blue
+      O_VGA_Pixel => O_Pixel
       );
+
+  O_Red   <= O_Pixel(2 downto 0);
+  O_Green <= O_Pixel(5 downto 3);
+  O_Blue  <= O_Pixel(7 downto 6);
+
   I_CLK <= not I_CLK after clk_period/2;
 
 end;