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Refactors VGA timing and mode handling

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Renames and restructures VGA timing generator for clarity and modularity.
Introduces VGA modes package for centralized resolution and timing configuration.
Updates related testbenches and constraints to align with new structure.
Improves maintainability and flexibility for future VGA mode additions.
This commit is contained in:
0xMax42
2025-04-26 10:26:52 +00:00
parent 319b51bf56
commit a73f125357
13 changed files with 404 additions and 223 deletions
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25
src/XY_Generator.vhd
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@@ -2,15 +2,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.VGA_Modes_Pkg.all;
entity XY_Generator is
generic (
G_X : integer := 640;
G_Y : integer := 480;
--@ Width of the X position (Row) register
G_X_Width : integer := 10;
--@ Width of the Y position (Line) register
G_Y_Width : integer := 10
--@ VGA Mode (0-9) from VGA_Modes_Pkg
G_VGA_Mode : integer := 2
);
port (
--@ Clock; (**Rising edge** triggered)
@@ -23,12 +20,12 @@ entity XY_Generator is
--@ @virtualbus Y @dir Out Output of the Y positions, with priority over X
O_Y_Valid : out std_logic;
I_Y_Ready : in std_logic;
O_Y : out std_logic_vector(G_Y_Width - 1 downto 0);
O_Y : out std_logic_vector(K_VGA_Modes(G_VGA_Mode).Y_Width - 1 downto 0);
--@ @end
--@ @virtualbus Y @dir Out Output of the X positions
O_X_Valid : out std_logic;
I_X_Ready : in std_logic;
O_X : out std_logic_vector(G_X_Width - 1 downto 0)
O_X : out std_logic_vector(K_VGA_Modes(G_VGA_Mode).X_Width - 1 downto 0)
--@ @end
);
@@ -36,8 +33,12 @@ entity XY_Generator is
end entity XY_Generator;
architecture RTL of XY_Generator is
signal R_X_Counter : unsigned(G_X_Width - 1 downto 0) := (others => '0');
signal R_Y_Counter : unsigned(G_Y_Width - 1 downto 0) := (others => '0');
constant K_X : integer := K_VGA_Modes(G_VGA_Mode).X_Resolution;
constant K_Y : integer := K_VGA_Modes(G_VGA_Mode).Y_Resolution;
signal R_X_Counter : unsigned(K_VGA_Modes(G_VGA_Mode).X_Width - 1 downto 0) := (others => '0');
signal R_Y_Counter : unsigned(K_VGA_Modes(G_VGA_Mode).Y_Width - 1 downto 0) := (others => '0');
signal R_Y_Valid : std_logic := '1';
signal R_X_Valid : std_logic := '1';
@@ -64,11 +65,11 @@ begin
R_X_Valid <= '0';
end if;
else
if R_X_Counter = (G_X - 1) then
if R_X_Counter = (K_X - 1) then
R_X_Counter <= (others => '0');
R_X_Valid <= '1';
if R_Y_Counter = (G_Y - 1) then
if R_Y_Counter = (K_Y - 1) then
R_Y_Counter <= (others => '0');
R_Y_Valid <= '1';
else