Refactors VGA timing and mode handling

Renames and restructures VGA timing generator for clarity and modularity.
Introduces VGA modes package for centralized resolution and timing configuration.
Updates related testbenches and constraints to align with new structure.
Improves maintainability and flexibility for future VGA mode additions.

project.cfg

@@ -2,7 +2,7 @@
 
 # Project name
 # @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = VGATimingGenerator
+PROJECT = VGA
 
 # Target device
 # @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
@@ -12,10 +12,10 @@ TARGET_PART = xc3s1200e-4-fg320
 XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 
 # Optional the name of the top module (default is the project name)
-TOPLEVEL = VGATimingGenerator_test
+TOPLEVEL = VGA_test
 
 # Optional the path/name of the ucf file (default is the project name)
-CONSTRAINTS = src/VGATimingGenerator_test.ucf
+CONSTRAINTS = src/VGA_test.ucf
 
 # Optional a target to copy the bit file to (make copy)
 # COPY_TARGET_DIR = 
@@ -29,10 +29,11 @@ CONSTRAINTS = src/VGATimingGenerator_test.ucf
 # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
 
 # VHDSOURCE += src/VGATimingGenerator_pb.vhd
-VHDSOURCE += src/VGATimingGenerator_test.vhd
-VHDSOURCE += src/VGATimingGenerator.vhd
+VHDSOURCE += src/VGA_test.vhd
+VHDSOURCE += src/Timing_Generator.vhd
 VHDSOURCE += src/XY_Generator.vhd
 VHDSOURCE += src/VGA.vhd
+VHDSOURCE += src/VGA_Modes_Pkg.vhd
 VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/GrayCounter.vhd
 VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/src/AsyncFIFO.vhd
 VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd