Consolidates VGA output signals into a single pixel bus

Replaces separate VGA Red, Green, and Blue output signals with a unified 8-bit VGA pixel bus for improved signal management.
Updates signal mapping, testbench, and constraints file to reflect the new structure.

Enhances maintainability and reduces signal complexity.

src/VGA.vhd

@@ -24,12 +24,8 @@ entity VGA is
         O_VGA_HSync : out std_logic;
         --@ Vertical Sync signal; **Active low**
         O_VGA_VSync : out std_logic;
-        --@ VGA Red Channel
+        --@ VGA Pixel Data: 3 bits Red, 3 bits Green, 2 bits Blue
-        O_VGA_Red   : out std_logic_vector(2 downto 0);
+        O_VGA_Pixel : out std_logic_vector(7 downto 0);
-        --@ VGA Green Channel
-        O_VGA_Green : out std_logic_vector(2 downto 0);
-        --@ VGA Blue Channel
-        O_VGA_Blue  : out std_logic_vector(1 downto 0);
         --@ @end
 
         --@ @virtualbus XY-Request @dir Out Request for the X and Y positions
@@ -63,6 +59,10 @@ architecture RTL of VGA is
     signal O_AsyncPixelDataFIFO_Data    : std_logic_vector(7 downto 0);
     signal C_DisablePixelOutput         : std_logic := '0';
 
+    signal O_VGA_Red   : std_logic_vector(2 downto 0) := (others => '0');
+    signal O_VGA_Green : std_logic_vector(2 downto 0) := (others => '0');
+    signal O_VGA_Blue  : std_logic_vector(1 downto 0) := (others => '0');
+
     -- Error signals --
     signal R_Error               : std_logic_vector(7 downto 0) := (others => '0');
     --@ Is set if the pixel data is requested but not available in the FIFO
@@ -81,6 +81,10 @@ begin
     O_VGA_HSync <= O_TimingGenerator_HSync;
     O_VGA_VSync <= O_TimingGenerator_VSync;
 
+    O_VGA_Pixel(2 downto 0) <= O_VGA_Red;
+    O_VGA_Pixel(5 downto 3) <= O_VGA_Green;
+    O_VGA_Pixel(7 downto 6) <= O_VGA_Blue;
+
     C_DisablePixelOutput <= not O_TimingGenerator_HSync and
                             not O_TimingGenerator_VSync;
 

src/VGATimingGenerator_test.ucf

@@ -2,14 +2,14 @@ NET I_CLK	                    LOC = B8;
 NET I_CLK	                TNM_NET = CLOCK;
 TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
 
-NET O_HSync	                LOC = T4 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_HSync	            LOC = T4 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_VSync	                LOC = U3 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_VSync	            LOC = U3 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
 
-NET O_Red<0>	            LOC = R9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<0>          LOC = R9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Red<1>	            LOC = T8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<1>          LOC = T8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Red<2>	            LOC = R8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<2>          LOC = R8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Green<0>	            LOC = N8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<3>          LOC = N8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Green<1>	            LOC = P8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<4>          LOC = P8 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Green<2>	            LOC = P6 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<5>          LOC = P6 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Blue<0>	            LOC = U5 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<6>          LOC = U5 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
-NET O_Blue<1>	            LOC = U4 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+NET O_VGA_Pixel<7>          LOC = U4 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;

src/VGATimingGenerator_test.vhd

@@ -9,16 +9,13 @@ entity VGATimingGenerator_test is
         I_CLK       : in  std_logic;
         --@ @virtualbus VGA-Signals @dir out VGA signals
         --@ Horizontal Sync signal; **Active low**
-        O_HSync : out std_logic;
+        O_VGA_HSync : out std_logic;
         --@ Vertical Sync signal; **Active low**
-        O_VSync : out std_logic;
+        O_VGA_VSync : out std_logic;
-        --@ VGA Red Channel
+        --@ VGA Pixel Data: 3 bits Red, 3 bits Green, 2 bits Blue
-        O_Red   : out std_logic_vector(2 downto 0);
+        O_VGA_Pixel : out std_logic_vector(7 downto 0)
-        --@ VGA Green Channel
-        O_Green : out std_logic_vector(2 downto 0);
-        --@ VGA Blue Channel
-        O_Blue  : out std_logic_vector(1 downto 0)
         --@ @end
+
         );
 end entity VGATimingGenerator_test;
 
@@ -151,11 +148,9 @@ begin
             I_VGA_PixelCLK        => I_CLK,
             I_VGA_PixelCE         => I_VGA_PixelCE,
             I_VGA_PixelRST        => I_VGA_PixelRST,
-            O_VGA_HSync           => O_HSync,
+            O_VGA_HSync           => O_VGA_HSync,
-            O_VGA_VSync           => O_VSync,
+            O_VGA_VSync           => O_VGA_VSync,
-            O_VGA_Red             => O_Red,
+            O_VGA_Pixel           => O_VGA_Pixel,
-            O_VGA_Green           => O_Green,
-            O_VGA_Blue            => O_Blue,
             I_VGA_CLK             => I_CLK,
             I_VGA_CE              => I_VGA_CE,
             I_VGA_RST             => I_VGA_RST,

tests/VGATimingGenerator_test_tb.vhd

@@ -22,8 +22,8 @@ begin
   VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
     port map (
       I_CLK       => I_CLK,
-    O_HSync => O_HSync,
+      O_VGA_HSync => O_HSync,
-    O_VSync => O_VSync,
+      O_VGA_VSync => O_VSync,
       O_Red       => O_Red,
       O_Green     => O_Green,
       O_Blue      => O_Blue