Reorganizes pipeline logic into distinct stages for clarity
Replaces monolithic process with modular components
Introduces AXI-like interface for better integration
Improves readability and maintainability by renaming signals
Updates visibility and offset calculations to use pipeline registers
Adds modules for sprite operations, including opcode decoding, register handling, and vertical pipeline calculations. Replaces legacy scheduler with a more modular and efficient design. Updates constraints for clock timing.
Enhances sprite rendering pipeline with improved modularity and scalability.
Defines constants for various sprite-related operations, including no-op, setting sprite ID, position, requesting row data, and clearing all. Provides a standardized set of codes for use in VHDL designs.
Replaces CalcPipeline with HorizontalSpritePipeline for improved
readability and maintainability. Introduces a structured pipeline
architecture with enhanced visibility checks, ROM access efficiency,
and modular design principles.
Provides better handling of non-visible pixels and adheres to
AXI-like handshake standards.
Implements various priority encoder components with combinatorial logic for encoding input vectors to output codes of varying widths.
Introduces pipeline-based modules for handling calculation, ROM data fetching, and scheduling operations with AXI-like handshaking interfaces.
Facilitates modular and reusable design for priority encoding and data processing tasks.
