MaxP 3c641355fc Introduces sprite channel processing pipeline
Adds modules for sprite operations, including opcode decoding, register handling, and vertical pipeline calculations. Replaces legacy scheduler with a more modular and efficient design. Updates constraints for clock timing.

Enhances sprite rendering pipeline with improved modularity and scalability.
2025-04-21 15:25:12 +00:00
Description
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818 KiB
Languages
VHDL 100%