Introduces sprite channel processing pipeline
Adds modules for sprite operations, including opcode decoding, register handling, and vertical pipeline calculations. Replaces legacy scheduler with a more modular and efficient design. Updates constraints for clock timing. Enhances sprite rendering pipeline with improved modularity and scalability.
This commit is contained in:
232
src/SpriteChannel.vhd
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232
src/SpriteChannel.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity SpriteChannel is
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generic (
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--@ Data width of the operation data.
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G_OPCodeData_Width : integer := 10;
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--@ Width of the sprite index (Base address) register
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G_Index_Width : integer := 5;
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--@ Width of the sprite offset (Line address) register
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G_Offset_Width : integer := 8;
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--@ Width of the X position (Row) register
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G_X_Width : integer := 10;
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--@ Width of the Y position (Line) register
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G_Y_Width : integer := 10;
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--@ The height of the sprite in pixels
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G_Sprite_Height : integer := 16;
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--@ The width of the sprite in pixels
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G_Sprite_Width : integer := 16
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);
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port (
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--@ Clock signal; **Rising edge** triggered
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I_CLK : in std_logic;
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--@ Clock Enable signal
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I_CE : in std_logic;
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--@ Synchronous reset signal
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I_RST : in std_logic;
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--@ @virtualbus Operation-Write @dir in Operation Write Interface
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--@ Indicates if the `OPCode` and `OPData` are valid. (**Active high**)
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I_OP_Valid : in std_logic := '0';
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--@ Indicates if the decoder is ready to accept data. (**Active high**)
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O_OP_Ready : out std_logic := '0';
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--@ Operation code for the sprite channel
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I_OP_Code : in std_logic_vector(3 downto 0) := (others => '0');
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--@ Data to be used with the operation code.
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I_OP_Data : in std_logic_vector(G_OPCodeData_Width - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus Pixel-Data @dir Out Pixel data output bus
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Pixel_Valid : out std_logic;
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Pixel_Ready : in std_logic;
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--@ Pixel data
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O_Pixel_Data : out std_logic_vector(7 downto 0)
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--@ @end
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);
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end entity;
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architecture RTL of SpriteChannel is
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signal R_Index : std_logic_vector(G_Index_Width - 1 downto 0) := (others => '0');
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signal R_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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signal R_X : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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signal R_Y : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
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signal R_IsVisible : std_logic := '0';
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signal OI_P0_Address_Valid : std_logic := '0';
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signal IO_P0_Address_Ready : std_logic := '0';
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signal OI_P0_Address : std_logic_vector(G_Index_Width + G_Offset_Width - 1 downto 0) := (others => '0');
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signal IO_P0_Data_Valid : std_logic := '0';
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signal OI_P0_Data_Ready : std_logic := '0';
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signal IO_P0_Data : std_logic_vector(7 downto 0) := (others => '0');
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signal OI_Register_Index_WE : std_logic := '0';
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signal OI_Register_Index : std_logic_vector(G_Index_Width - 1 downto 0) := (others => '0');
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signal OI_Register_Offset_WE : std_logic := '0';
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signal OI_Register_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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signal OI_Register_X_We : std_logic := '0';
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signal OI_Register_X : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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signal OI_Register_Y_WE : std_logic := '0';
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signal OI_Register_Y : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
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signal OI_IsVisible_WE : std_logic := '0';
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signal OI_IsVisible : std_logic := '0';
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signal I_YHitCheck_Ready : std_logic := '0';
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signal I_YHitCheck_Valid : std_logic := '0';
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signal I_YHitCheck_IsVisible : std_logic := '0';
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signal I_YHitCheck_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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signal O_YHitCheck_Valid : std_logic := '0';
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signal O_YHitCheck_YToCheck : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
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signal O_YHitCheck_Ready : std_logic := '0';
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signal OI_CalcPipeline_Valid : std_logic := '0';
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signal IO_CalcPipeline_Ready : std_logic := '0';
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signal OI_CalcPipeline_X_Request : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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begin
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i_RegisterFile : entity work.RegisterFile
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generic map(
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G_Index_Width => G_Index_Width,
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G_Offset_Width => G_Offset_Width,
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G_X_Width => G_X_Width,
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G_Y_Width => G_Y_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_Index_WE => OI_Register_Index_WE,
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I_Index => OI_Register_Index,
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I_Offset_WE => OI_Register_Offset_WE,
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I_Offset => OI_Register_Offset,
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I_X_We => OI_Register_X_We,
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I_X => OI_Register_X,
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I_Y_WE => OI_Register_Y_WE,
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I_Y => OI_Register_Y,
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I_IsVisible_WE => OI_IsVisible_WE,
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I_IsVisible => OI_IsVisible,
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O_Index => R_Index,
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O_Offset => R_Offset,
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O_X => R_X,
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O_Y => R_Y,
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O_IsVisible => R_IsVisible
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);
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i_OPDecoder : entity work.OPDecoder
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generic map(
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G_OPCodeData_Width => G_OPCodeData_Width,
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G_Index_Width => G_Index_Width,
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G_Offset_Width => G_Offset_Width,
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G_X_Width => G_X_Width,
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G_Y_Width => G_Y_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_OP_Valid => I_OP_Valid,
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O_OP_Ready => O_OP_Ready,
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I_OP_Code => I_OP_Code,
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I_OP_Data => I_OP_Data,
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O_Register_Index_WE => OI_Register_Index_WE,
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O_Register_Index => OI_Register_Index,
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O_Register_Offset_WE => OI_Register_Offset_WE,
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O_Register_Offset => OI_Register_Offset,
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O_Register_X_We => OI_Register_X_We,
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O_Register_X => OI_Register_X,
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O_Register_Y_WE => OI_Register_Y_WE,
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O_Register_Y => OI_Register_Y,
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O_IsVisible_WE => OI_IsVisible_WE,
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O_IsVisible => OI_IsVisible,
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I_IsVisible => R_IsVisible,
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I_YHitCheck_Ready => I_YHitCheck_Ready,
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O_YHitCheck_Valid => O_YHitCheck_Valid,
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O_YHitCheck_YToCheck => O_YHitCheck_YToCheck,
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O_YHitCheck_Ready => O_YHitCheck_Ready,
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I_YHitCheck_Valid => I_YHitCheck_Valid,
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I_YHitCheck_IsVisible => I_YHitCheck_IsVisible,
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I_YHitCheck_Offset => I_YHitCheck_Offset,
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O_HSpritePipeline_Valid => OI_CalcPipeline_Valid,
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I_HSpritePipeline_Ready => IO_CalcPipeline_Ready,
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O_HSpritePipeline_X_Request => OI_CalcPipeline_X_Request
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);
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i_YHitCheck : entity work.VerticalSpritePipeline
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generic map(
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G_Y_Width => G_Y_Width,
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G_Sprite_Height => G_Sprite_Height,
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G_Offset_Width => G_Offset_Width,
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G_PipelineStages => 2
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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O_Ready => I_YHitCheck_Ready,
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I_Valid => O_YHitCheck_Valid,
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I_YToCheck => O_YHitCheck_YToCheck,
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I_Y => R_Y,
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I_Ready => O_YHitCheck_Ready,
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O_Valid => I_YHitCheck_Valid,
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O_IsVisible => I_YHitCheck_IsVisible,
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O_Offset => I_YHitCheck_Offset
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);
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i_Rom : entity work.Rom
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generic map(
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G_Address_Width => 13,
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G_Data_Width => 8,
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G_P0_BufferStages => 1,
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G_P0_ID_Width => 0,
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G_P1_BufferStages => 0,
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G_P1_ID_Width => 0,
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G_RomType => "Block"
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_P0_Address_Valid => OI_P0_Address_Valid,
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O_P0_Address_Ready => IO_P0_Address_Ready,
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I_P0_Address => OI_P0_Address,
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O_P0_Data_Valid => IO_P0_Data_Valid,
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I_P0_Data_Ready => OI_P0_Data_Ready,
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O_P0_Data => IO_P0_Data
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);
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i_CalcPipeline : entity work.HorizontalSpritePipeline
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generic map(
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G_Index_Width => G_Index_Width,
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G_Offset_Width => G_Offset_Width,
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G_X_Width => G_X_Width,
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G_Rom_Width => 8,
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G_Pixel_Width => 8
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_OP_Valid => OI_CalcPipeline_Valid,
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O_OP_Ready => IO_CalcPipeline_Ready,
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I_OP_X_Request => OI_CalcPipeline_X_Request,
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I_OP_Index => R_Index,
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I_OP_Offset => R_Offset,
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I_OP_X_Sprite => R_X,
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O_Rom_Valid => OI_P0_Address_Valid,
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I_Rom_Ready => IO_P0_Address_Ready,
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O_Rom_Address => OI_P0_Address,
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I_Rom_Valid => IO_P0_Data_Valid,
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O_Rom_Ready => OI_P0_Data_Ready,
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I_Rom_Data => IO_P0_Data,
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O_Pixel_Valid => O_Pixel_Valid,
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I_Pixel_Ready => I_Pixel_Ready,
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O_Pixel_Data => O_Pixel_Data
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);
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end architecture RTL;
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