generated from maxp/FPGA-Devcontainer-Xilinx
45 lines
1020 B
VHDL
45 lines
1020 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity SPU_tb is
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end entity SPU_tb;
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architecture RTL of SPU_tb is
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-- Clock period
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constant K_CLKPeriod : time := 20 ns;
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signal I_CLK : std_logic;
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signal O_HSync : std_logic;
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signal O_VSync : std_logic;
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signal O_Red : std_logic_vector(2 downto 0);
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signal O_Green : std_logic_vector(2 downto 0);
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signal O_Blue : std_logic_vector(1 downto 0);
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begin
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ClockProc : process
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begin
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while true loop
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I_CLK <= '0';
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wait for K_CLKPeriod / 2;
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I_CLK <= '1';
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wait for K_CLKPeriod / 2;
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end loop;
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wait;
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end process;
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i_SPU : entity work.SPU
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port map(
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I_CLK => I_CLK,
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O_HSync => O_HSync,
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O_VSync => O_VSync,
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O_Red => O_Red,
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O_Green => O_Green,
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O_Blue => O_Blue
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);
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end architecture;
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