library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity SPU_tb is
end entity SPU_tb;

architecture RTL of SPU_tb is
    -- Clock period
    constant K_CLKPeriod : time := 20 ns;
    signal I_CLK         : std_logic;
    signal O_HSync       : std_logic;
    signal O_VSync       : std_logic;
    signal O_Red         : std_logic_vector(2 downto 0);
    signal O_Green       : std_logic_vector(2 downto 0);
    signal O_Blue        : std_logic_vector(1 downto 0);

begin

    ClockProc : process
    begin
        while true loop
            I_CLK <= '0';
            wait for K_CLKPeriod / 2;
            I_CLK <= '1';
            wait for K_CLKPeriod / 2;
        end loop;

        wait;
    end process;

    i_SPU : entity work.SPU
        port map(
            I_CLK   => I_CLK,
            O_HSync => O_HSync,
            O_VSync => O_VSync,
            O_Red   => O_Red,
            O_Green => O_Green,
            O_Blue  => O_Blue
            );


end architecture;