feat(vscode): add custom color theme settings

- Updates the devcontainer image to a newer version.
- Modifies the GPG agent path for consistency.
- Adds the WakaTime extension for tracking development time.
- Updates the postStartCommand to install hdlbuild from a
  private package repository.

.devcontainer/devcontainer.json

@@ -1,18 +1,19 @@
 {
   "name": "Xilinx ISE 14.7",
-  "image": "xilinx-ise:14.7",
+  "image": "git.0xmax42.io/simdev/xilinx-ise:latest",
   "runArgs": [
     "--privileged",
     "--cap-add=SYS_ADMIN",
     "--shm-size=2g",
     "-v",
-    "/run/user/1000/gnupg/S.gpg-agent:/run/user/1000/gnupg/S.gpg-agent"
+    "/run/user/1000/gnupg/S.gpg-agent:/home/xilinx/.gnupg/S.gpg-agent"
   ],
   "customizations": {
     "vscode": {
       "extensions": [
         "/home/xilinx/vsxirepo/vhdl-by-hgb.vsix",
-        "eamodio.gitlens"
+        "eamodio.gitlens",
+        "WakaTime.vscode-wakatime"
       ],
       "settings": {
         "terminal.integrated.defaultProfile.linux": "bash"
@@ -26,5 +27,5 @@
   "forwardPorts": [
     10000
   ],
-  "postStartCommand": "git config --global user.signingkey 87C8A5DD5C14DF55DBE1DB4199AC216D447E61C0 && git config --global gpg.format openpgp && git config --global commit.gpgsign true && git config --global tag.forceSignAnnotated true && sudo apt update && sudo apt upgrade -y"
+  "postStartCommand": "git config --global user.signingkey 87C8A5DD5C14DF55DBE1DB4199AC216D447E61C0 && git config --global gpg.format openpgp && git config --global commit.gpgsign true && git config --global tag.forceSignAnnotated true && pip install --upgrade --index-url https://git.0xmax42.io/api/packages/maxp/pypi/simple/ --extra-index-url https://pypi.org/simple/ hdlbuild"
 }

.vscode/settings.json

@@ -0,0 +1,12 @@
+{
+    "workbench.colorCustomizations": {
+        "activityBar.activeBackground": "#9ed8bc",
+        "activityBar.background": "#9ed8bc",
+        "activityBar.foreground": "#15202b",
+        "activityBar.inactiveForeground": "#15202b99",
+        "activityBarBadge.background": "#a177c8",
+        "activityBarBadge.foreground": "#15202b"
+    },
+    "peacock.color": "#7ac9a3",
+    "peacock.remoteColor": "#e67338"
+}

src/PipelineBufferController.vhd

@@ -41,7 +41,6 @@ architecture RTL of PipelineBufferController is
     signal C_Enable : std_logic := '0';
 
     signal R_IsBuffered : std_logic := '0';
-    signal R_Ready      : std_logic := '1';
 begin
 
     --@ Set mux to buffered mode if data is available in the buffer.
@@ -51,21 +50,19 @@ begin
     --@ Set the valid signal to high if data is available in the buffer or if data is valid.
     O_Valid  <= R_IsBuffered or I_Valid;
 
-    O_Ready <= R_Ready;
-
     process (I_CLK)
     begin
         if rising_edge(I_CLK) then
             if I_RST = G_ResetActiveAt then
                 R_IsBuffered <= '0';
-                R_Ready      <= '1';
+                O_Ready      <= '1';
             elsif I_CE = '1' then
                 if R_IsBuffered = '0' and I_Valid = '1' then
                     R_IsBuffered <= '1';
-                    R_Ready      <= '0';
+                    O_Ready      <= '0';
                 elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
                     R_IsBuffered <= '0';
-                    R_Ready      <= '1';
+                    O_Ready      <= '1';
                 end if;
             end if;
         end if;

src/Pipeline_pb_Module.vhd

@@ -30,9 +30,11 @@ entity Pipeline_pb_Module is
         I_CLK   : in  std_logic;
         I_RST   : in  std_logic;
         I_CE    : in  std_logic;
+        ---
         I_Data  : in  std_logic_vector(G_Width - 1 downto 0);
         I_Valid : in  std_logic;
         O_Ready : out std_logic;
+        ---
         O_Data  : out std_logic_vector(G_Width - 1 downto 0);
         O_Valid : out std_logic;
         I_Ready : in  std_logic
@@ -40,7 +42,7 @@ entity Pipeline_pb_Module is
 end entity Pipeline_pb_Module;
 
 architecture RTL of Pipeline_pb_Module is
-    signal C_Pipeline0Enable      : std_logic;
+    signal C_PipelineEnable       : std_logic;
     signal C_PipelineBufferEnable : std_logic_vector(1 downto 0) := (others => '0');
 
     signal R_Valid : std_logic;
@@ -48,7 +50,7 @@ architecture RTL of Pipeline_pb_Module is
     signal R_Data  : std_logic_vector(G_Width - 1 downto 0);
     signal C_Data  : std_logic_vector(G_Width - 1 downto 0);
 begin
-    PipelineControllerIn : entity work.PipelineController
+    INST_PipelineControllerIn : entity work.PipelineController
         generic map(
             G_PipelineStages => G_PipelineStages,
             G_ResetActiveAt  => '1'
@@ -57,14 +59,14 @@ begin
             I_CLK    => I_CLK,
             I_RST    => I_RST,
             I_CE     => I_CE,
-            O_Enable => C_Pipeline0Enable,
+            O_Enable => C_PipelineEnable,
             I_Valid  => I_Valid,
             O_Ready  => O_Ready,
             O_Valid  => R_Valid,
             I_Ready  => R_Ready
             );
 
-    PipelineRegisterIn : entity work.PipelineRegister
+    INST_PipelineRegisterIn : entity work.PipelineRegister
         generic map(
             G_PipelineStages    => G_PipelineStages,
             G_Width             => G_Width,
@@ -72,7 +74,7 @@ begin
             )
         port map(
             I_CLK    => I_CLK,
-            I_Enable => C_Pipeline0Enable,
+            I_Enable => C_PipelineEnable,
             I_Data   => I_Data,
             O_Data   => R_Data
             );
@@ -84,8 +86,8 @@ begin
     ---------
 
     -- Pipeline Buffer Generation based on G_EnablePipelineBuffer
-    gen_pipeline_buffer : if G_EnablePipelineBuffer generate
-        PipelineBufferController : entity work.PipelineBufferController
+    GEN_PipelineBuffer : if G_EnablePipelineBuffer generate
+        INST_PipelineBufferController : entity work.PipelineBufferController
             generic map(
                 G_ResetActiveAt => '1'
                 )
@@ -100,7 +102,7 @@ begin
                 I_Ready  => I_Ready
                 );
 
-        PipelineBuffer : entity work.PipelineBuffer
+        INST_PipelineBuffer : entity work.PipelineBuffer
             generic map(
                 G_Width => G_Width
                 )
@@ -110,14 +112,13 @@ begin
                 I_Data   => C_Data,
                 O_Data   => O_Data
                 );
-    end generate gen_pipeline_buffer;
+    end generate GEN_PipelineBuffer;
 
     -- Direct connection when pipeline buffer is disabled
-    gen_direct_connection : if not G_EnablePipelineBuffer generate
-        -- Direct signal connections (bypass pipeline buffer)
+    GEN_PassthroughWithoutBuffer : if not G_EnablePipelineBuffer generate
         O_Valid <= R_Valid;
         O_Data  <= R_Data;
         R_Ready <= I_Ready;
-    end generate gen_direct_connection;
+    end generate GEN_PassthroughWithoutBuffer;
 
 end architecture RTL;