125 lines
4.2 KiB
VHDL
125 lines
4.2 KiB
VHDL
--@ Performance Benchmarking Environment
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--@ This file is a wrapper for the module which is to be tested
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--@ and capsulates the module with flip-flops to create a synchronous
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--@ interface for the module. This is necessary to test the synthesis
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--@ results of the module.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity Pipeline_pb_Module is
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generic (
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--@ Number of pipeline stages
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G_PipelineStages : integer := 10;
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--@ Data width
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G_Width : integer := 32;
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--@ Register balancing attribute<br>
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--@ - "no" : No register balancing <br>
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--@ - "yes": Register balancing in both directions <br>
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--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
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--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "no";
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--@ Enable pipeline buffer
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--@ - true : Use pipeline buffer
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--@ - false : Direct connection (bypass)
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G_EnablePipelineBuffer : boolean := false
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);
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port (
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I_CLK : in std_logic;
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I_RST : in std_logic;
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I_CE : in std_logic;
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---
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I_Data : in std_logic_vector(G_Width - 1 downto 0);
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I_Valid : in std_logic;
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O_Ready : out std_logic;
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---
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O_Data : out std_logic_vector(G_Width - 1 downto 0);
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O_Valid : out std_logic;
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I_Ready : in std_logic
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);
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end entity Pipeline_pb_Module;
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architecture RTL of Pipeline_pb_Module is
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signal C_PipelineEnable : std_logic;
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signal C_PipelineBufferEnable : std_logic_vector(1 downto 0) := (others => '0');
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signal R_Valid : std_logic;
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signal R_Ready : std_logic;
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signal R_Data : std_logic_vector(G_Width - 1 downto 0);
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signal C_Data : std_logic_vector(G_Width - 1 downto 0);
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begin
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INST_PipelineControllerIn : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => I_RST,
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I_CE => I_CE,
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O_Enable => C_PipelineEnable,
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I_Valid => I_Valid,
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O_Ready => O_Ready,
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O_Valid => R_Valid,
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I_Ready => R_Ready
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);
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INST_PipelineRegisterIn : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_PipelineEnable,
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I_Data => I_Data,
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O_Data => R_Data
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);
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---------
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C_Data <= std_logic_vector(unsigned(R_Data) + 3); -- Example operation, can be replaced with actual logic
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---------
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-- Pipeline Buffer Generation based on G_EnablePipelineBuffer
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GEN_PipelineBuffer : if G_EnablePipelineBuffer generate
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INST_PipelineBufferController : entity work.PipelineBufferController
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generic map(
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => I_RST,
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I_CE => I_CE,
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O_Enable => C_PipelineBufferEnable,
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I_Valid => R_Valid,
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O_Ready => R_Ready,
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O_Valid => O_Valid,
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I_Ready => I_Ready
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);
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INST_PipelineBuffer : entity work.PipelineBuffer
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generic map(
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G_Width => G_Width
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_PipelineBufferEnable,
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I_Data => C_Data,
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O_Data => O_Data
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);
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end generate GEN_PipelineBuffer;
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-- Direct connection when pipeline buffer is disabled
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GEN_PassthroughWithoutBuffer : if not G_EnablePipelineBuffer generate
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O_Valid <= R_Valid;
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O_Data <= R_Data;
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R_Ready <= I_Ready;
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end generate GEN_PassthroughWithoutBuffer;
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end architecture RTL;
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