HDL/Pipeline-AXI-Handshake
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refactor: adjusts pipeline parameters for performance

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- Changes clock frequency to 280 MHz.
- Reduces pipeline module count to improve performance.
This commit is contained in:
0xMax42
2025-07-11 10:15:49 +00:00
parent 88753b62f4
commit 5e1a3c2161
2 changed files with 2 additions and 2 deletions
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2
src/Pipeline_pb.ucf
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@@ -1,4 +1,4 @@
#NET I_CLK LOC = AG18; #NET I_CLK LOC = AG18;
NET I_CLK LOC = B8; NET I_CLK LOC = B8;
NET I_CLK TNM_NET = CLOCK; NET I_CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %; TIMESPEC TS_CLOCK = PERIOD CLOCK 280 MHz HIGH 50 %;

2
src/Pipeline_pb.vhd
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@@ -26,7 +26,7 @@ entity Pipeline_pb is
--@ - false : Direct connection (bypass) --@ - false : Direct connection (bypass)
G_EnablePipelineBuffer : boolean := true; G_EnablePipelineBuffer : boolean := true;
--@ How many Pipeline modules shall be chained? --@ How many Pipeline modules shall be chained?
G_PipelineModules : integer := 250; G_PipelineModules : integer := 20;
--@ Enable chip enable signal --@ Enable chip enable signal
G_Enable_CE : boolean := false; G_Enable_CE : boolean := false;
--@ Enable reset signal --@ Enable reset signal