Configured the project with a specific name, target part, and constraints file. Added VHDL source and testbench files for the GenericCounter module. Additionally, set up ISIM commands for VCD file dumping and execution control during simulation. These changes prepare the project for the forthcoming development and testing of the GenericCounter component on a designated FPGA device.
The Generic Counter VHDL module has been added under `src`, providing a configurable digital counter with synchronous reset, clock enable, set priority, over/underflow flag, and up/down counting capabilities. This addition includes detailed documentation and a waveform for simulation purposes, signifying an emphasis on maintainability and verification via the included Testbench, which has passed simulation.
