Updated project configuration with GenericCounter specifics

Configured the project with a specific name, target part, and constraints file. Added VHDL source and testbench files for the GenericCounter module. Additionally, set up ISIM commands for VCD file dumping and execution control during simulation. These changes prepare the project for the forthcoming development and testing of the GenericCounter component on a designated FPGA device.

project.cfg

@@ -2,11 +2,11 @@
 
 # Project name
 # @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = 
+PROJECT = GenericCounter
 
 # Target device
 # @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
-TARGET_PART = 
+TARGET_PART = xc5vlx50t-1-ff1136
 
 # Path to the Xilinx ISE installation
 XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
@@ -15,7 +15,7 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # TOPLEVEL = 
 
 # Optional the name of the ucf file (default is the project name)
-# CONSTRAINTS = 
+CONSTRAINTS = src/GenericCounter.ucf
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -25,6 +25,8 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # @example `VSOURCE += src/main.v` (add a single Verilog file per line)
 # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
 
+VHDSOURCE += src/GenericCounter.vhd
+VHDTEST += tests/GenericCounter_tb.vhd
 
 
 ## ## ## ## ## ## ## ##
@@ -32,6 +34,8 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 
 ## ISE executable settings.. ##
 
+ISIM_CMD = vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun 1 us\nvcd dumpflush\nquit
+
 # General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
 # COMMON_OPTS = 
 # Options for the XST synthesizer