diff --git a/build b/build
index d7eebb6..a8ed470 160000
--- a/build
+++ b/build
@@ -1 +1 @@
-Subproject commit d7eebb6517061ec1a29d49a56cf5fe3423a667bd
+Subproject commit a8ed470e7de04ce923360ec480f3087795f136d6
diff --git a/project.cfg b/project.cfg
index a59cde5..f697eef 100644
--- a/project.cfg
+++ b/project.cfg
@@ -2,11 +2,11 @@
 
 # Project name
 # @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = 
+PROJECT = GenericCounter
 
 # Target device
 # @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
-TARGET_PART = 
+TARGET_PART = xc5vlx50t-1-ff1136
 
 # Path to the Xilinx ISE installation
 XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
@@ -15,7 +15,7 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # TOPLEVEL = 
 
 # Optional the name of the ucf file (default is the project name)
-# CONSTRAINTS = 
+CONSTRAINTS = src/GenericCounter.ucf
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -25,6 +25,8 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # @example `VSOURCE += src/main.v` (add a single Verilog file per line)
 # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
 
+VHDSOURCE += src/GenericCounter.vhd
+VHDTEST += tests/GenericCounter_tb.vhd
 
 
 ## ## ## ## ## ## ## ##
@@ -32,6 +34,8 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 
 ## ISE executable settings.. ##
 
+ISIM_CMD = vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun 1 us\nvcd dumpflush\nquit
+
 # General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
 # COMMON_OPTS = 
 # Options for the XST synthesizer