Enhanced the GenericCounter VHDL module by adding a comprehensive set of features, including synchronous reset, clock enable, configurable counting direction, over- and underflow flags, and lookahead value. Introduced detailed project documentation, including a descriptive README, waveform diagrams in both SVG and JSON format, and a UCF constraints file specifying clock settings.
Introduced a new VHDL testbench for the GenericCounter component, complete with initial signal declarations, a clock process, and a stimulus process to emulate different scenarios and edge cases. The inclusion of generics and port mappings ensures the testbench's flexibility to simulate counter behavior under various conditions. Accompanying the testbench, a wave configuration file has been added to aid in simulation analysis, allowing for visualization and easier debugging of the component's states during simulation runs.
Configured the project with a specific name, target part, and constraints file. Added VHDL source and testbench files for the GenericCounter module. Additionally, set up ISIM commands for VCD file dumping and execution control during simulation. These changes prepare the project for the forthcoming development and testing of the GenericCounter component on a designated FPGA device.
The Generic Counter VHDL module has been added under `src`, providing a configurable digital counter with synchronous reset, clock enable, set priority, over/underflow flag, and up/down counting capabilities. This addition includes detailed documentation and a waveform for simulation purposes, signifying an emphasis on maintainability and verification via the included Testbench, which has passed simulation.
