HDL/GenericCounter
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refactor(entity): rename generics and ports for clarity

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- Standardizes naming conventions for generics and ports
- Improves readability and consistency across the entity architecture
This commit is contained in:
0xMax42
2025-07-07 12:24:38 +00:00
parent 685e94e8ae
commit c86249d4b3
1 changed files with 38 additions and 38 deletions
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76
src/GenericCounter.vhd
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@@ -96,88 +96,88 @@ use ieee.math_real.all;
entity GenericCounter is entity GenericCounter is
generic ( generic (
--@ Width of the counter --@ Width of the counter
Width : integer := 4; G_Width : integer := 4;
--@ Initial value of the counter --@ Initial value of the counter
InitialValue : integer := 0; G_InitialValue : integer := 0;
--@ Reset value of the counter --@ Reset value of the counter
ResetValue : integer := 0; G_ResetValue : integer := 0;
--@ Counting direction: "UP" or "DOWN" --@ Counting direction: "UP" or "DOWN"
CountingDirection : string := "UP"; G_CountingDirection : string := "UP";
--@ Look ahead value --@ Look ahead value
LookAhead : integer := 0 G_LookAhead : integer := 0
); );
port ( port (
--@ Clock input; rising edge --@ Clock input; rising edge
CLK : in std_logic; I_CLK : in std_logic;
--@ Reset input; active high; synchronous --@ Reset input; active high; synchronous
RST : in std_logic; I_RST : in std_logic;
--@ Clock enable; active high --@ Clock enable; active high
CE : in std_logic; I_CE : in std_logic;
--@ Count enable; active high --@ Count enable; active high
CountEnable : in std_logic; I_CountEnable : in std_logic;
--@ Counter Value --@ Counter Value
CounterValue : out std_logic_vector(Width - 1 downto 0); O_CounterValue : out std_logic_vector(G_Width - 1 downto 0);
--@ Look ahead value --@ Look ahead value
LookAheadValue : out std_logic_vector(Width - 1 downto 0); O_LookAheadValue : out std_logic_vector(G_Width - 1 downto 0);
--@ Set with priority over the `CountEnable` --@ Set with priority over the `CountEnable`
Set : in std_logic; I_Set : in std_logic;
--@ If set is high, the counter will be set to SetValue --@ If set is high, the counter will be set to SetValue
SetValue : in std_logic_vector(Width - 1 downto 0); I_SetValue : in std_logic_vector(G_Width - 1 downto 0);
--@ Over- and Underflow flag --@ Over- and Underflow flag
OverUnderflow : out std_logic O_OverUnderflow : out std_logic
); );
end entity GenericCounter; end entity GenericCounter;
architecture RTL of GenericCounter is architecture RTL of GenericCounter is
function CountingStep(BinaryValue : unsigned; Step : integer := 1) function CountingStep(BinaryValue : unsigned; Step : integer := 1)
return unsigned is return unsigned is
begin begin
if CountingDirection = "UP" then if G_CountingDirection = "UP" then
return BinaryValue + Step; return BinaryValue + Step;
else else
return BinaryValue - Step; return BinaryValue - Step;
end if; end if;
end function CountingStep; end function CountingStep;
signal R_Counter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width); signal R_Counter : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
signal C_NextCounter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width); signal C_NextCounter : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
signal C_LookAhead : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue + LookAhead, Width); signal C_LookAhead : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue + G_LookAhead, G_Width);
signal C_OverUnderflow : std_logic; signal C_OverUnderflow : std_logic;
begin begin
process (CLK) process (I_CLK)
begin begin
if rising_edge(CLK) then if rising_edge(I_CLK) then
if RST = '1' then if I_RST = '1' then
R_Counter <= to_unsigned(ResetValue, Width); R_Counter <= to_unsigned(G_ResetValue, G_Width);
elsif CE = '1' then elsif I_CE = '1' then
R_Counter <= C_NextCounter; R_Counter <= C_NextCounter;
end if; end if;
end if; end if;
end process; end process;
Counting : process (R_Counter, CountEnable, Set, SetValue) Counting : process (R_Counter, I_CountEnable, I_Set, I_SetValue)
variable V_OverUnderflow : unsigned(Width downto 0); variable V_OverUnderflow : unsigned(G_Width downto 0);
begin begin
V_OverUnderflow := CountingStep("0" & R_Counter); V_OverUnderflow := CountingStep("0" & R_Counter);
if Set = '1' then if I_Set = '1' then
C_NextCounter <= unsigned(SetValue); C_NextCounter <= unsigned(I_SetValue);
C_LookAhead <= CountingStep(unsigned(SetValue), LookAhead); C_LookAhead <= CountingStep(unsigned(I_SetValue), G_LookAhead);
C_OverUnderflow <= '0'; C_OverUnderflow <= '0';
elsif CountEnable = '1' then elsif I_CountEnable = '1' then
C_NextCounter <= V_OverUnderflow(Width - 1 downto 0); C_NextCounter <= V_OverUnderflow(G_Width - 1 downto 0);
C_LookAhead <= CountingStep(R_Counter, 1 + LookAhead); C_LookAhead <= CountingStep(R_Counter, 1 + G_LookAhead);
C_OverUnderflow <= V_OverUnderflow(Width); C_OverUnderflow <= V_OverUnderflow(G_Width);
else else
C_NextCounter <= R_Counter; C_NextCounter <= R_Counter;
C_LookAhead <= CountingStep(R_Counter, LookAhead); C_LookAhead <= CountingStep(R_Counter, G_LookAhead);
C_OverUnderflow <= '0'; C_OverUnderflow <= '0';
end if; end if;
end process; end process;
LookAheadValue <= std_logic_vector(C_LookAhead); O_LookAheadValue <= std_logic_vector(C_LookAhead);
CounterValue <= std_logic_vector(C_NextCounter); O_CounterValue <= std_logic_vector(C_NextCounter);
OverUnderflow <= C_OverUnderflow; O_OverUnderflow <= C_OverUnderflow;
end architecture RTL; end architecture RTL;