refactor(entity): rename generics and ports for clarity
- Standardizes naming conventions for generics and ports - Improves readability and consistency across the entity architecture
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@@ -96,88 +96,88 @@ use ieee.math_real.all;
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entity GenericCounter is
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generic (
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--@ Width of the counter
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Width : integer := 4;
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G_Width : integer := 4;
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--@ Initial value of the counter
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InitialValue : integer := 0;
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G_InitialValue : integer := 0;
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--@ Reset value of the counter
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ResetValue : integer := 0;
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G_ResetValue : integer := 0;
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--@ Counting direction: "UP" or "DOWN"
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CountingDirection : string := "UP";
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G_CountingDirection : string := "UP";
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--@ Look ahead value
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LookAhead : integer := 0
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);
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G_LookAhead : integer := 0
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);
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port (
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--@ Clock input; rising edge
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CLK : in std_logic;
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I_CLK : in std_logic;
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--@ Reset input; active high; synchronous
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RST : in std_logic;
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I_RST : in std_logic;
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--@ Clock enable; active high
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CE : in std_logic;
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I_CE : in std_logic;
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--@ Count enable; active high
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CountEnable : in std_logic;
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I_CountEnable : in std_logic;
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--@ Counter Value
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CounterValue : out std_logic_vector(Width - 1 downto 0);
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O_CounterValue : out std_logic_vector(G_Width - 1 downto 0);
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--@ Look ahead value
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LookAheadValue : out std_logic_vector(Width - 1 downto 0);
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O_LookAheadValue : out std_logic_vector(G_Width - 1 downto 0);
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--@ Set with priority over the `CountEnable`
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Set : in std_logic;
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I_Set : in std_logic;
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--@ If set is high, the counter will be set to SetValue
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SetValue : in std_logic_vector(Width - 1 downto 0);
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I_SetValue : in std_logic_vector(G_Width - 1 downto 0);
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--@ Over- and Underflow flag
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OverUnderflow : out std_logic
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);
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O_OverUnderflow : out std_logic
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);
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end entity GenericCounter;
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architecture RTL of GenericCounter is
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function CountingStep(BinaryValue : unsigned; Step : integer := 1)
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return unsigned is
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begin
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if CountingDirection = "UP" then
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if G_CountingDirection = "UP" then
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return BinaryValue + Step;
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else
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return BinaryValue - Step;
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end if;
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end function CountingStep;
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signal R_Counter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
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signal C_NextCounter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
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signal C_LookAhead : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue + LookAhead, Width);
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signal R_Counter : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
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signal C_NextCounter : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
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signal C_LookAhead : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue + G_LookAhead, G_Width);
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signal C_OverUnderflow : std_logic;
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begin
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process (CLK)
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process (I_CLK)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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R_Counter <= to_unsigned(ResetValue, Width);
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elsif CE = '1' then
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if rising_edge(I_CLK) then
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if I_RST = '1' then
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R_Counter <= to_unsigned(G_ResetValue, G_Width);
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elsif I_CE = '1' then
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R_Counter <= C_NextCounter;
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end if;
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end if;
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end process;
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Counting : process (R_Counter, CountEnable, Set, SetValue)
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variable V_OverUnderflow : unsigned(Width downto 0);
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Counting : process (R_Counter, I_CountEnable, I_Set, I_SetValue)
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variable V_OverUnderflow : unsigned(G_Width downto 0);
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begin
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V_OverUnderflow := CountingStep("0" & R_Counter);
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if Set = '1' then
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C_NextCounter <= unsigned(SetValue);
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C_LookAhead <= CountingStep(unsigned(SetValue), LookAhead);
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if I_Set = '1' then
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C_NextCounter <= unsigned(I_SetValue);
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C_LookAhead <= CountingStep(unsigned(I_SetValue), G_LookAhead);
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C_OverUnderflow <= '0';
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elsif CountEnable = '1' then
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C_NextCounter <= V_OverUnderflow(Width - 1 downto 0);
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C_LookAhead <= CountingStep(R_Counter, 1 + LookAhead);
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C_OverUnderflow <= V_OverUnderflow(Width);
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elsif I_CountEnable = '1' then
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C_NextCounter <= V_OverUnderflow(G_Width - 1 downto 0);
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C_LookAhead <= CountingStep(R_Counter, 1 + G_LookAhead);
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C_OverUnderflow <= V_OverUnderflow(G_Width);
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else
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C_NextCounter <= R_Counter;
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C_LookAhead <= CountingStep(R_Counter, LookAhead);
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C_LookAhead <= CountingStep(R_Counter, G_LookAhead);
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C_OverUnderflow <= '0';
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end if;
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end process;
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LookAheadValue <= std_logic_vector(C_LookAhead);
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CounterValue <= std_logic_vector(C_NextCounter);
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OverUnderflow <= C_OverUnderflow;
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O_LookAheadValue <= std_logic_vector(C_LookAhead);
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O_CounterValue <= std_logic_vector(C_NextCounter);
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O_OverUnderflow <= C_OverUnderflow;
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end architecture RTL;
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