From c86249d4b34284e66921bfebd85fb7ccfdceeacd Mon Sep 17 00:00:00 2001
From: Max P <mail@0xMax42.io>
Date: Mon, 7 Jul 2025 12:24:38 +0000
Subject: [PATCH] refactor(entity): rename generics and ports for clarity

- Standardizes naming conventions for generics and ports
- Improves readability and consistency across the entity architecture
---
 src/GenericCounter.vhd | 76 +++++++++++++++++++++---------------------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/src/GenericCounter.vhd b/src/GenericCounter.vhd
index 96bf05d..5f92d5f 100644
--- a/src/GenericCounter.vhd
+++ b/src/GenericCounter.vhd
@@ -96,88 +96,88 @@ use ieee.math_real.all;
 entity GenericCounter is
     generic (
         --@ Width of the counter
-        Width : integer := 4;
+        G_Width             : integer := 4;
         --@ Initial value of the counter
-        InitialValue : integer := 0;
+        G_InitialValue      : integer := 0;
         --@ Reset value of the counter
-        ResetValue : integer := 0;
+        G_ResetValue        : integer := 0;
         --@ Counting direction: "UP" or "DOWN"
-        CountingDirection : string := "UP";
+        G_CountingDirection : string  := "UP";
         --@ Look ahead value
-        LookAhead : integer := 0
-    );
+        G_LookAhead         : integer := 0
+        );
     port (
         --@ Clock input; rising edge
-        CLK : in std_logic;
+        I_CLK            : in  std_logic;
         --@ Reset input; active high; synchronous
-        RST : in std_logic;
+        I_RST            : in  std_logic;
         --@ Clock enable; active high
-        CE : in std_logic;
+        I_CE             : in  std_logic;
         --@ Count enable; active high
-        CountEnable : in std_logic;
+        I_CountEnable    : in  std_logic;
         --@ Counter Value
-        CounterValue : out std_logic_vector(Width - 1 downto 0);
+        O_CounterValue   : out std_logic_vector(G_Width - 1 downto 0);
         --@ Look ahead value
-        LookAheadValue : out std_logic_vector(Width - 1 downto 0);
+        O_LookAheadValue : out std_logic_vector(G_Width - 1 downto 0);
         --@ Set with priority over the `CountEnable`
-        Set : in std_logic;
+        I_Set            : in  std_logic;
         --@ If set is high, the counter will be set to SetValue
-        SetValue : in std_logic_vector(Width - 1 downto 0);
+        I_SetValue       : in  std_logic_vector(G_Width - 1 downto 0);
         --@ Over- and Underflow flag
-        OverUnderflow : out std_logic
-    );
+        O_OverUnderflow  : out std_logic
+        );
 end entity GenericCounter;
 
 architecture RTL of GenericCounter is
     function CountingStep(BinaryValue : unsigned; Step : integer := 1)
         return unsigned is
     begin
-        if CountingDirection = "UP" then
+        if G_CountingDirection = "UP" then
             return BinaryValue + Step;
         else
             return BinaryValue - Step;
         end if;
     end function CountingStep;
 
-    signal R_Counter       : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
-    signal C_NextCounter   : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
-    signal C_LookAhead     : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue + LookAhead, Width);
+    signal R_Counter       : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
+    signal C_NextCounter   : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue, G_Width);
+    signal C_LookAhead     : unsigned(G_Width - 1 downto 0) := to_unsigned(G_InitialValue + G_LookAhead, G_Width);
     signal C_OverUnderflow : std_logic;
 begin
 
-    process (CLK)
+    process (I_CLK)
     begin
-        if rising_edge(CLK) then
-            if RST = '1' then
-                R_Counter <= to_unsigned(ResetValue, Width);
-            elsif CE = '1' then
+        if rising_edge(I_CLK) then
+            if I_RST = '1' then
+                R_Counter <= to_unsigned(G_ResetValue, G_Width);
+            elsif I_CE = '1' then
                 R_Counter <= C_NextCounter;
             end if;
         end if;
     end process;
 
-    Counting : process (R_Counter, CountEnable, Set, SetValue)
-        variable V_OverUnderflow : unsigned(Width downto 0);
+    Counting : process (R_Counter, I_CountEnable, I_Set, I_SetValue)
+        variable V_OverUnderflow : unsigned(G_Width downto 0);
     begin
         V_OverUnderflow := CountingStep("0" & R_Counter);
 
-        if Set = '1' then
-            C_NextCounter   <= unsigned(SetValue);
-            C_LookAhead     <= CountingStep(unsigned(SetValue), LookAhead);
+        if I_Set = '1' then
+            C_NextCounter   <= unsigned(I_SetValue);
+            C_LookAhead     <= CountingStep(unsigned(I_SetValue), G_LookAhead);
             C_OverUnderflow <= '0';
-        elsif CountEnable = '1' then
-            C_NextCounter   <= V_OverUnderflow(Width - 1 downto 0);
-            C_LookAhead     <= CountingStep(R_Counter, 1 + LookAhead);
-            C_OverUnderflow <= V_OverUnderflow(Width);
+        elsif I_CountEnable = '1' then
+            C_NextCounter   <= V_OverUnderflow(G_Width - 1 downto 0);
+            C_LookAhead     <= CountingStep(R_Counter, 1 + G_LookAhead);
+            C_OverUnderflow <= V_OverUnderflow(G_Width);
         else
             C_NextCounter   <= R_Counter;
-            C_LookAhead     <= CountingStep(R_Counter, LookAhead);
+            C_LookAhead     <= CountingStep(R_Counter, G_LookAhead);
             C_OverUnderflow <= '0';
         end if;
     end process;
 
-    LookAheadValue <= std_logic_vector(C_LookAhead);
-    CounterValue   <= std_logic_vector(C_NextCounter);
-    OverUnderflow  <= C_OverUnderflow;
+    O_LookAheadValue <= std_logic_vector(C_LookAhead);
+    O_CounterValue   <= std_logic_vector(C_NextCounter);
+    O_OverUnderflow  <= C_OverUnderflow;
 
 end architecture RTL;