Updated the DEPP VHDL interface entity and architecture to version 0.3.0, adding detailed annotations and a timing diagram for clarity. Standard library usage declarations have been optimized. Entity and architecture names, along with various signals, have been renamed to reflect the Digilent EPP interface standards. A description and history section has been included to improve documentation. Function `log2_ceil` is refined to `min_bits_for_states` for better semantic understanding. Port and signal names now adhere to the DEPP nomenclature for consistency with the Digilent Adept software. Additional comments have been added throughout to describe interface functions and signal usage more clearly.
Max P
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