Max P dce101dfdf feat(rob): add reorder buffer entity with slot management ...

- Introduces a VHDL implementation for a reorder buffer (ROB)
- Adds generic parameters for slot depth, ID width, and data width
- Implements synchronous reset, clock enable, and data flow logic
- Improves modularity with pipeline stage instantiation

2025-07-07 13:14:53 +00:00

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