Max P
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- Introduces a VHDL implementation for a reorder buffer (ROB) - Adds generic parameters for slot depth, ID width, and data width - Implements synchronous reset, clock enable, and data flow logic - Improves modularity with pipeline stage instantiation
111 lines
3.9 KiB
VHDL
111 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity ROB is
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generic (
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G_SlotDepth : integer := 1;
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G_IDWidth : integer := 3;
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G_DataWidth : integer := 10
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);
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port (
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--@ Clock; (**Rising edge** triggered)
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I_CLK : in std_logic := '0';
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--@ Clock Enable; (**Synchronous**, **Active high**)
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I_CE : in std_logic := '1';
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--@ Reset; (**Synchronous**, **Active high**)
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I_RST : in std_logic := '0';
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--@ AXI like valid; (**Synchronous**, **Active high**)
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I_Valid : in std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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O_Ready : out std_logic := '0';
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--@ Data input
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I_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '-');
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I_ID : in std_logic_vector(G_IDWidth - 1 downto 0) := (others => '0');
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Valid : out std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Ready : in std_logic := '0';
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--@ Data output
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O_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '-');
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O_ReadPointer : out std_logic_vector(G_IDWidth - 1 downto 0) := (others => '0')
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);
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end entity ROB;
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architecture RTL of ROB is
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constant K_IDDepth : integer := 2**G_IDWidth;
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signal R_ReadPointer : std_logic_vector(G_IDWidth - 1 downto 0) := (others => '0');
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signal C_ReadPointerEnable : std_logic := '0';
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type T_Data is array (0 to K_IDDepth -1) of std_logic_vector(G_DataWidth-1 downto 0);
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type T_Flag is array (0 to K_IDDepth -1) of std_logic;
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signal R_O_Data : T_Data := (others => (others => '0'));
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signal C_O_Valid : T_Flag := (others => '0');
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signal C_I_Ready : T_Flag := (others => '0');
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signal C_I_Valid : T_Flag := (others => '0');
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signal C_O_Ready : T_Flag := (others => '0');
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begin
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P_ReadPointer : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_RST = '1' then
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R_ReadPointer <= (others => '0');
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elsif I_CE = '1' then
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if C_ReadPointerEnable = '1' then
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R_ReadPointer <= std_logic_vector(unsigned(R_ReadPointer) + 1);
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end if;
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end if;
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end if;
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end process;
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O_ReadPointer <= R_ReadPointer;
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C_ReadPointerEnable <= I_Ready and C_O_Valid(to_integer(unsigned(R_ReadPointer)));
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O_Data <= R_O_Data(to_integer(unsigned(R_ReadPointer)));
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O_Valid <= C_O_Valid(to_integer(unsigned(R_ReadPointer)));
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P_OutputReadyMux : process (R_ReadPointer, I_Ready)
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begin
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C_I_Ready <= (others => '0');
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C_I_Ready(to_integer(unsigned(R_ReadPointer))) <= I_Ready;
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end process;
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GEN_SlotRegister : for i in 0 to K_IDDepth -1 generate
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begin
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INST_SlotRegister : entity work.PipelineStage
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generic map(
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G_PipelineStages => G_SlotDepth,
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G_D0_Width => G_DataWidth
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_Valid => C_I_Valid(i),
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O_Ready => C_O_Ready(i),
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I_Data_0 => I_Data,
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O_Valid => C_O_Valid(i),
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I_Ready => C_I_Ready(i),
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O_Data_0 => R_O_Data(i)
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);
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end generate;
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O_Ready <= C_O_Ready(to_integer(unsigned(I_ID)));
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P_InputValidMux : process (I_ID, I_Valid)
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begin
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C_I_Valid <= (others => '0');
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C_I_Valid(to_integer(unsigned(I_ID))) <= I_Valid;
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end process;
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end architecture;
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