2 Commits

Author	SHA1	Message	Date
Max P	880526968f	feat(src): define clock constraints in ROB.ucf ... - Adds clock net mapping and timing specifications - Defines a 200 MHz clock period with 50% duty cycle	2025-07-07 13:15:01 +00:00
Max P	dce101dfdf	feat(rob): add reorder buffer entity with slot management ... - Introduces a VHDL implementation for a reorder buffer (ROB) - Adds generic parameters for slot depth, ID width, and data width - Implements synchronous reset, clock enable, and data flow logic - Improves modularity with pipeline stage instantiation	2025-07-07 13:14:53 +00:00