MaxP
2fce367686
- Introduced new scripts for project generation and synthesis (dodo.py, generate_prj.py, generate_scr.py, run_xst.py). - Implemented configuration parsing for VHDL sources and project settings (config.py). - Added default configuration values (defaults.py). - Updated .gitignore to include additional file types. - Created test cases for project generation and configuration parsing (test_generate_prj.py, test_generate_scr.py, test_project_cfg.py).
52 lines
1.7 KiB
Python
52 lines
1.7 KiB
Python
from build.tools.config import parse_project_cfg
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from pathlib import Path
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import tempfile
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import textwrap
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def test_parse_complex_project_cfg_correctly():
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cfg = textwrap.dedent("""
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## Main settings.. ##
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PROJECT = SpriteChannel
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TARGET_PART = xc3s1200e-4-fg320
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XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
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TOPLEVEL = SpriteChannel
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CONSTRAINTS = src/SpriteChannel.ucf
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# Sources (should be ignored)
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VHDSOURCE += src/GenericCounter.vhd
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VSOURCE += src/something.v
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VHDTEST += test/SpriteChannel_tb.vhd
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# Options
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XST_OPTS += -opt_mode Speed
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XST_OPTS += -opt_level 2
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MAP_OPTS = -detail -timing -ol high
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PAR_OPTS = -ol high
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BITGEN_OPTS = -g StartupClk:JtagClk
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# Programmer
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PROGRAMMER = digilent
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""")
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with tempfile.NamedTemporaryFile("w+", suffix=".cfg", delete=False) as f:
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f.write(cfg)
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f.flush()
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result = parse_project_cfg(Path(f.name))
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assert result["PROJECT"] == "SpriteChannel"
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assert result["TARGET_PART"] == "xc3s1200e-4-fg320"
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assert result["XILINX"] == "/opt/Xilinx/14.7/ISE_DS/ISE"
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assert result["TOPLEVEL"] == "SpriteChannel"
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assert result["CONSTRAINTS"] == "src/SpriteChannel.ucf"
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assert result["XST_OPTS"] == "-opt_mode Speed -opt_level 2"
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assert result["MAP_OPTS"] == "-detail -timing -ol high"
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assert result["PAR_OPTS"] == "-ol high"
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assert result["BITGEN_OPTS"] == "-g StartupClk:JtagClk"
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assert result["PROGRAMMER"] == "digilent"
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# Sicherstellen, dass SOURCE-Felder ignoriert wurden
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assert "VHDSOURCE" not in result
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assert "VSOURCE" not in result
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assert "VHDTEST" not in result
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