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2 Commits

Author SHA1 Message Date
Max P.
93d441531d Add HDL elements and interfaces for VHDL types, generics, functions, procedures, constants, variables, assignments, and ports 2025-04-02 19:52:28 +02:00
Max P.
19180d4516 Base configuration 2025-03-29 22:55:08 +01:00