SpriteChannel/src/RegisterFile.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity RegisterFile is
    generic (
        --@ Width of the sprite index (Base address) register
        G_Index_Width  : integer := 5;
        --@ Width of the sprite offset (Line address) register
        G_Offset_Width : integer := 8;
        --@ Width of the X position (Row) register
        G_X_Width      : integer := 10;
        --@ Width of the Y position (Line) register
        G_Y_Width      : integer := 10
    );
    port (
        --@ Clock signal; (**Rising edge** triggered)
        I_CLK          : in  std_logic;
        --@ Clock enable signal (**Active high**)
        I_CE           : in  std_logic                                     := '1';
        --@ Synchronous reset signal (**Active high**)
        I_RST          : in  std_logic                                     := '0';

        --@ @virtualbus Register-Write @dir in Bus to write to the register file
        --@ Write enable for the sprite index register; (**Active high**)
        I_Index_WE     : in  std_logic                                     := '0';
        --@ Data to write to the sprite index (Base address) register.
        I_Index        : in  std_logic_vector(G_Index_Width - 1 downto 0)  := (others => '0');
        --@ Write enable for the sprite offset (line) register; (**Active high**)
        I_Offset_WE    : in  std_logic                                     := '0';
        --@ Data to write to the sprite offset (Line address) register.
        I_Offset       : in  std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
        --@ Write enable for the X position register. (**Active high**)
        I_X_We         : in  std_logic                                     := '0';
        --@ Data to write to the X position register (Row) of the sprite.
        I_X            : in  std_logic_vector(G_X_Width - 1 downto 0)      := (others => '0');
        --@ Write enable for the Y position register. (**Active high**)
        I_Y_WE         : in  std_logic                                     := '0';
        --@ Data to write to the Y position register (Line) of the sprite.
        I_Y            : in  std_logic_vector(G_Y_Width - 1 downto 0)      := (others => '0');
        --@ Write enable for the `IsVisible` flag. (**Active high**)
        I_IsVisible_WE : in  std_logic                                     := '0';
        --@ Flag to write to the `IsVisible` flag.
        I_IsVisible    : in  std_logic                                     := '0';

        --@ @virtualbus Register-Read @dir out Bus to read from the register file
        --@ Sprite index (Base address) of the sprite.
        O_Index        : out std_logic_vector(G_Index_Width - 1 downto 0)  := (others => '0');
        --@ Sprite offset (Line address) of the sprite.
        O_Offset       : out std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
        --@ X position of the sprite.
        O_X            : out std_logic_vector(G_X_Width - 1 downto 0)      := (others => '0');
        --@ Y position of the sprite.
        O_Y            : out std_logic_vector(G_Y_Width - 1 downto 0)      := (others => '0');
        --@ Flag to indicate if the sprite line is valid; (**Active high**)
        O_IsVisible    : out std_logic                                     := '0'
        --@ @end
    );
end entity;

architecture RTL of RegisterFile is
    --@ Register for the sprite index (Base address).
    signal R_Index     : std_logic_vector(G_Index_Width - 1 downto 0)  := (others => '0');
    --@ Register for the sprite offset (Line address).
    signal R_Offset    : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
    --@ Register for the X position (Row) of the sprite.
    signal R_X         : std_logic_vector(G_X_Width - 1 downto 0)      := (others => '0');
    --@ Register for the Y position (Line) of the sprite.
    signal R_Y         : std_logic_vector(G_Y_Width - 1 downto 0)      := (others => '0');
    --@ Register for the `IsVisible` flag.
    signal R_IsVisible : std_logic                                     := '0';
begin

    --@ Register file process  
    P_RegisterFile : process (I_CLK)
    begin
        if rising_edge(I_CLK) then
            if I_RST = '1' then
                R_Index     <= (others => '0');
                R_Offset    <= (others => '0');
                R_X         <= (others => '0');
                R_Y         <= (others => '0');
                R_IsVisible <= '0';
            elsif I_CE = '1' then
                if I_Index_WE = '1' then
                    R_Index <= I_Index;
                end if;

                if I_Offset_WE = '1' then
                    R_Offset <= I_Offset;
                end if;

                if I_X_We = '1' then
                    R_X <= I_X;
                end if;

                if I_Y_WE = '1' then
                    R_Y <= I_Y;
                end if;

                if I_IsVisible_WE = '1' then
                    R_IsVisible <= I_IsVisible;
                end if;
            end if;
        end if;
    end process;

    --@ Forwarding the register values to the output
    P_Forwarding : process (
        R_Index, R_Offset, R_X, R_Y,
        R_IsVisible
        )
    begin
        O_Index     <= R_Index;
        O_Offset    <= R_Offset;
        O_X         <= R_X;
        O_Y         <= R_Y;
        O_IsVisible <= R_IsVisible;
    end process;

end architecture;