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| 87422e3dcc |
30
.devcontainer/devcontainer.json
Normal file
30
.devcontainer/devcontainer.json
Normal file
@@ -0,0 +1,30 @@
|
||||
{
|
||||
"name": "Xilinx ISE 14.7",
|
||||
"image": "xilinx-ise:14.7",
|
||||
"runArgs": [
|
||||
"--privileged",
|
||||
"--cap-add=SYS_ADMIN",
|
||||
"--shm-size=2g",
|
||||
"-v",
|
||||
"/run/user/1000/gnupg/S.gpg-agent:/run/user/1000/gnupg/S.gpg-agent"
|
||||
],
|
||||
"customizations": {
|
||||
"vscode": {
|
||||
"extensions": [
|
||||
"/home/xilinx/vsxirepo/vhdl-by-hgb.vsix",
|
||||
"eamodio.gitlens"
|
||||
],
|
||||
"settings": {
|
||||
"terminal.integrated.defaultProfile.linux": "bash"
|
||||
}
|
||||
}
|
||||
},
|
||||
"remoteUser": "xilinx",
|
||||
"workspaceMount": "source=${localWorkspaceFolder},target=/workspaces/${localWorkspaceFolderBasename},type=bind",
|
||||
"workspaceFolder": "/workspaces/${localWorkspaceFolderBasename}",
|
||||
"features": {},
|
||||
"forwardPorts": [
|
||||
10000
|
||||
],
|
||||
"postStartCommand": "git config --global user.signingkey 87C8A5DD5C14DF55DBE1DB4199AC216D447E61C0 && git config --global gpg.format openpgp && git config --global commit.gpgsign true && git config --global tag.forceSignAnnotated true && sudo apt update && sudo apt upgrade -y"
|
||||
}
|
||||
9
.github/workflows/build.yml
vendored
9
.github/workflows/build.yml
vendored
@@ -1,4 +1,4 @@
|
||||
name: Manuelles Build mit ISE
|
||||
name: Build with HDLBuild
|
||||
|
||||
on:
|
||||
workflow_dispatch:
|
||||
@@ -9,9 +9,12 @@ jobs:
|
||||
steps:
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
submodules: true
|
||||
|
||||
- name: Build
|
||||
run: |
|
||||
cd "$GITHUB_WORKSPACE/build"
|
||||
make
|
||||
cd "$GITHUB_WORKSPACE"
|
||||
hdlbuild dep
|
||||
hdlbuild build
|
||||
|
||||
|
||||
5
.gitignore
vendored
5
.gitignore
vendored
@@ -1 +1,6 @@
|
||||
.hdlbuild_deps/
|
||||
.working/
|
||||
reports/
|
||||
output/
|
||||
.locale/
|
||||
vhdl_ls.toml
|
||||
6
.gitmodules
vendored
6
.gitmodules
vendored
@@ -1,6 +0,0 @@
|
||||
[submodule "libs/AXI-HS-MUX"]
|
||||
path = libs/AXI-HS-MUX
|
||||
url = ssh://git@git.0xmax42.io:33612/maxp/AXI-HS-MUX.git
|
||||
[submodule "libs/AXI-HS-Scheduler"]
|
||||
path = libs/AXI-HS-Scheduler
|
||||
url = ssh://git@git.0xmax42.io:33612/maxp/AXI-HS-Scheduler.git
|
||||
2
build/.gitignore
vendored
2
build/.gitignore
vendored
@@ -1,2 +0,0 @@
|
||||
working/
|
||||
reports/
|
||||
@@ -1,24 +0,0 @@
|
||||
This is free and unencumbered software released into the public domain.
|
||||
|
||||
Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
distribute this software, either in source code form or as a compiled
|
||||
binary, for any purpose, commercial or non-commercial, and by any
|
||||
means.
|
||||
|
||||
In jurisdictions that recognize copyright laws, the author or authors
|
||||
of this software dedicate any and all copyright interest in the
|
||||
software to the public domain. We make this dedication for the benefit
|
||||
of the public at large and to the detriment of our heirs and
|
||||
successors. We intend this dedication to be an overt act of
|
||||
relinquishment in perpetuity of all present and future rights to this
|
||||
software under copyright law.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
For more information, please refer to <http://unlicense.org>
|
||||
275
build/Makefile
275
build/Makefile
@@ -1,275 +0,0 @@
|
||||
###########################################################################
|
||||
## Xilinx ISE Makefile
|
||||
##
|
||||
## To the extent possible under law, the author(s) have dedicated all copyright
|
||||
## and related and neighboring rights to this software to the public domain
|
||||
## worldwide. This software is distributed without any warranty.
|
||||
##
|
||||
## Makefile github repository: https://github.com/PxaMMaxP/Xilinx-ISE-Makefile
|
||||
###########################################################################
|
||||
|
||||
###########################################################################
|
||||
# Version
|
||||
###########################################################################
|
||||
|
||||
Makefile_Version := 1.1.5
|
||||
$(info ISE Makefile Version: $(Makefile_Version))
|
||||
|
||||
###########################################################################
|
||||
# Include project configuration
|
||||
###########################################################################
|
||||
|
||||
include ../project.cfg
|
||||
|
||||
###########################################################################
|
||||
# Default values
|
||||
###########################################################################
|
||||
|
||||
ifndef XILINX
|
||||
$(error XILINX must be defined)
|
||||
endif
|
||||
|
||||
ifndef PROJECT
|
||||
$(error PROJECT must be defined)
|
||||
endif
|
||||
|
||||
ifndef TARGET_PART
|
||||
$(error TARGET_PART must be defined)
|
||||
endif
|
||||
|
||||
TOPLEVEL ?= $(PROJECT)
|
||||
CONSTRAINTS ?= $(PROJECT).ucf
|
||||
BUILD_DIR ?= working
|
||||
REPORT_DIR ?= reports
|
||||
BITFILE ?= $(BUILD_DIR)/$(PROJECT).bit
|
||||
|
||||
COMMON_OPTS ?= -intstyle xflow
|
||||
XST_OPTS ?=
|
||||
NGDBUILD_OPTS ?=
|
||||
MAP_OPTS ?= -detail
|
||||
PAR_OPTS ?=
|
||||
BITGEN_OPTS ?=
|
||||
TRACE_OPTS ?= -v 3 -n 3
|
||||
FUSE_OPTS ?= -incremental
|
||||
|
||||
ISIM_OPTS ?= -gui
|
||||
ISIM_CMD ?=
|
||||
|
||||
PROGRAMMER ?= none
|
||||
PROGRAMMER_PRE ?=
|
||||
|
||||
IMPACT_OPTS ?= -batch impact.cmd
|
||||
|
||||
DJTG_EXE ?= djtgcfg
|
||||
DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
|
||||
DJTG_INDEX ?= 0
|
||||
DJTG_FLASH_INDEX ?= 1
|
||||
|
||||
XC3SPROG_EXE ?= xc3sprog
|
||||
XC3SPROG_CABLE ?= none
|
||||
XC3SPROG_OPTS ?=
|
||||
|
||||
|
||||
###########################################################################
|
||||
# Internal variables, platform-specific definitions, and macros
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
XILINX := $(shell cygpath -m $(XILINX))
|
||||
CYG_XILINX := $(shell cygpath $(XILINX))
|
||||
EXE := .exe
|
||||
XILINX_PLATFORM ?= nt64
|
||||
PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
|
||||
else
|
||||
EXE :=
|
||||
XILINX_PLATFORM ?= lin64
|
||||
PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
|
||||
endif
|
||||
|
||||
TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
|
||||
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
|
||||
|
||||
RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
|
||||
cd $(BUILD_DIR) && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
|
||||
|
||||
# isim executables don't work without this
|
||||
export XILINX
|
||||
|
||||
# Initialize the libs and paths variables for VHDL and Verilog sources
|
||||
VHD_PATHS ?=
|
||||
VHD_LIBS ?=
|
||||
V_PATHS ?=
|
||||
V_LIBS ?=
|
||||
|
||||
# Define a function to process source files
|
||||
define process_sources
|
||||
$(foreach src,$(1),\
|
||||
$(eval lib_and_path=$(subst :, ,$(src))) \
|
||||
$(eval libname=$(word 1,$(lib_and_path))) \
|
||||
$(eval filepath=$(word 2,$(lib_and_path))) \
|
||||
$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
|
||||
$(eval $(2) += $(libname)) \
|
||||
$(eval $(3) += ../$(filepath)) \
|
||||
)
|
||||
endef
|
||||
|
||||
# Run the function for VHDL sources
|
||||
$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
|
||||
# Run the function for Verilog sources
|
||||
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
|
||||
|
||||
## Tests
|
||||
|
||||
# Initialize the libs and paths variables for VHDL and Verilog testbenches
|
||||
VHD_TEST_PATHS ?=
|
||||
VHD_TEST_LIBS ?=
|
||||
V_TEST_PATHS ?=
|
||||
V_TEST_LIBS ?=
|
||||
|
||||
# Run the function for VHDL tests
|
||||
$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
|
||||
# Run the function for Verilog tests
|
||||
$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
|
||||
|
||||
# Get the test names..
|
||||
TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
|
||||
TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
|
||||
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
|
||||
|
||||
###########################################################################
|
||||
# Default build
|
||||
###########################################################################
|
||||
|
||||
default: $(BITFILE)
|
||||
|
||||
clean:
|
||||
rm -rf $(BUILD_DIR)
|
||||
rm -rf $(REPORT_DIR)
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
|
||||
@echo "Updating $@"
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@mkdir -p $(REPORT_DIR)
|
||||
@rm -f $@
|
||||
@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
|
||||
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
|
||||
@cp $(BUILD_DIR)/$(PROJECT).prj $@
|
||||
@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
|
||||
@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
|
||||
@echo "Updating $@"
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@rm -f $@
|
||||
@echo "run" \
|
||||
"-ifn $(PROJECT).prj" \
|
||||
"-ofn $(PROJECT).ngc" \
|
||||
"-ifmt mixed" \
|
||||
"$(XST_OPTS)" \
|
||||
"-top $(TOPLEVEL)" \
|
||||
"-ofmt NGC" \
|
||||
"-p $(TARGET_PART)" \
|
||||
> $(BUILD_DIR)/$(PROJECT).scr
|
||||
|
||||
$(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj $(BUILD_DIR)/$(PROJECT).scr
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@mkdir -p $(REPORT_DIR)
|
||||
$(call RUN,xst) $(COMMON_OPTS) \
|
||||
-ifn $(PROJECT).scr
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).srp $(REPORT_DIR)/$(PROJECT).SynthesisReport
|
||||
$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
|
||||
-p $(TARGET_PART) -uc ../../$(CONSTRAINTS) \
|
||||
$(PROJECT).ngc $(PROJECT).ngd
|
||||
$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
|
||||
-p $(TARGET_PART) \
|
||||
-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).map.mrp $(REPORT_DIR)/$(PROJECT).MapReport
|
||||
$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
|
||||
-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).par $(REPORT_DIR)/$(PROJECT).PlaceRouteReport
|
||||
$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
|
||||
-w $(PROJECT).ncd $(PROJECT).bit
|
||||
@echo "\e[1;32m============ OK ============\e[m\n\n"
|
||||
@echo "\e[1;33m============ Reports.. ===========\e[m\n"
|
||||
@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).SynthesisReport\e[m\n"
|
||||
@echo "\e[1;97m======= Map Summary Report =======\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).MapReport\e[m\n"
|
||||
@echo "\e[1;97m======= PAR Summary Report =======\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PlaceRouteReport\e[m\n"
|
||||
@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT)_pad.txt $(REPORT_DIR)/$(PROJECT).PinoutReport
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PinoutReport\e[m\n"
|
||||
|
||||
copy: $(BITFILE)
|
||||
@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
|
||||
@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
|
||||
|
||||
###########################################################################
|
||||
# Testing (work in progress)
|
||||
###########################################################################
|
||||
|
||||
trace: ../project.cfg $(BITFILE)
|
||||
$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
|
||||
$(PROJECT).ncd $(PROJECT).pcf
|
||||
@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
|
||||
@echo "\e[1;97m===== Timing Summary Report ======\e[m"
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).twr $(REPORT_DIR)/$(PROJECT).TimingReport
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).TimingReport\e[m\n"
|
||||
|
||||
test: buildtest runtest
|
||||
|
||||
runtest: ${TEST_NAMES}
|
||||
|
||||
${TEST_NAMES}:
|
||||
@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
|
||||
@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
|
||||
cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
|
||||
|
||||
buildtest: ${TEST_EXES}
|
||||
|
||||
$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
|
||||
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
|
||||
-prj $(PROJECT)_sim.prj \
|
||||
-o isim_$*$(EXE) \
|
||||
work.$* work.glbl
|
||||
|
||||
|
||||
###########################################################################
|
||||
# Programming
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(PROGRAMMER), impact)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), xc3sprog)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), none)
|
||||
prog:
|
||||
$(error PROGRAMMER must be set to use 'make prog')
|
||||
endif
|
||||
|
||||
###########################################################################
|
||||
# Flash
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
flash: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
###########################################################################
|
||||
225
build/README.md
225
build/README.md
@@ -1,225 +0,0 @@
|
||||
# Xilinx ISE Makefile
|
||||
|
||||
Tired of clicking around in Xilinx ISE? Run your builds from the command line!
|
||||
|
||||
## Forked from..
|
||||
|
||||
The original project is located at [Xilinx-ISE-Makefile](https://github.com/duskwuff/Xilinx-ISE-Makefile) and was created by [duskwuff](github.com/duskwuff/).
|
||||
|
||||
Many thanks for the good work!
|
||||
|
||||
## Requirements
|
||||
|
||||
- Xilinx ISE, ideally 14.7 (the final version)
|
||||
|
||||
Works great on Linux. Windows Subsystem for Linux is tested and works well.
|
||||
|
||||
- GNU (or compatible?) Make
|
||||
|
||||
Install this through Cygwin on Windows.
|
||||
|
||||
## Creating a project
|
||||
|
||||
To start building a project, you will need to create a file `project.cfg` in
|
||||
the top level of your project. This file is a text file sourced by Make, so
|
||||
it consists of `KEY = value` pairs. It must define at least the following keys:
|
||||
|
||||
- `PROJECT`
|
||||
|
||||
The name of the project, used as a name for certain intermediate files, and
|
||||
as the default name for the top-level module and constraints file.
|
||||
|
||||
- `TARGET_PART`
|
||||
|
||||
The full part-speed-package identifier for the Xilinx part to be targeted,
|
||||
e.g. `xc6slx9-2-tqg144`.
|
||||
|
||||
- `XILINX`
|
||||
|
||||
The path to the appropriate binaries directory of the target Xilinx ISE
|
||||
install, e.g.
|
||||
`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE`
|
||||
or
|
||||
`/opt/Xilinx/14.7/ISE_DS/ISE`
|
||||
for typical installs.
|
||||
|
||||
- `VSOURCE` and/or `VHDSOURCE`
|
||||
|
||||
The space-separated names of all Verilog and/or VHDL source files to be
|
||||
used in the project.
|
||||
|
||||
You can define these on multiple lines using `+=`, e.g.
|
||||
|
||||
VSOURCE += foo.v
|
||||
VSOURCE += bar.v
|
||||
|
||||
You can also add a library name to the source file, e.g.
|
||||
|
||||
VSOURCE += my_lib:foo.v
|
||||
VSOURCE += my_lib:bar.v
|
||||
|
||||
The default library name is `work`.
|
||||
|
||||
A simple `project.cfg` may thus resemble:
|
||||
|
||||
PROJECT = example
|
||||
TARGET_PART = xc6slx9-2-cpg196
|
||||
|
||||
XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
|
||||
|
||||
VSOURCE = example.v
|
||||
|
||||
A number of other keys can be set in the project configuration, including:
|
||||
|
||||
- `XILINX_PLATFORM`
|
||||
|
||||
The Xilinx name for the platform to build for, e.g. `nt64` or `lin`.
|
||||
`nt64` is used by default for Windows systems, and `lin64` for Linux
|
||||
systems, so you only need to set this if you explicitly need to use the
|
||||
32-bit version of the tools for some reason.
|
||||
|
||||
- `TOPLEVEL`
|
||||
|
||||
The name of the top-level module to be used in the project.
|
||||
(Defaults to `$PROJECT`.)
|
||||
|
||||
- `CONSTRAINTS`
|
||||
|
||||
The name of the constraints file (`.ucf`) to be used for the project.
|
||||
(Defaults to `$PROJECT.ucf`.)
|
||||
|
||||
- `COMMON_OPTS`
|
||||
|
||||
Extra command-line options to be passed to all ISE executables. Defaults to
|
||||
`-intstyle xflow`.
|
||||
|
||||
- `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,
|
||||
`TRACE_OPTS`, `FUSE_OPTS`
|
||||
|
||||
Extra command-line options to be passed to the corresponding ISE tools.
|
||||
|
||||
Defaults is:
|
||||
|
||||
```
|
||||
XST_OPTS ?=
|
||||
NGDBUILD_OPTS ?=
|
||||
MAP_OPTS ?= -detail
|
||||
PAR_OPTS ?=
|
||||
BITGEN_OPTS ?=
|
||||
TRACE_OPTS ?= -v 3 -n 3
|
||||
FUSE_OPTS ?= -incremental
|
||||
```
|
||||
|
||||
Note that `XST_OPTS` will not appear on the command line during
|
||||
compilation, as the XST options are embedded in a script file.
|
||||
|
||||
`MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading,
|
||||
which may speed up compilation of large designs.
|
||||
|
||||
`BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression.
|
||||
|
||||
- `PROGRAMMER`
|
||||
|
||||
The name of the programmer to be used for `make prog`. Currently supported
|
||||
values are:
|
||||
|
||||
- `impact`
|
||||
|
||||
Uses Xilinx iMPACT for programming, using a batch file named
|
||||
`impact.cmd` by default. The iMPACT command line may be overridden by
|
||||
setting `IMPACT_OPTS`.
|
||||
|
||||
A typical batch file may resemble:
|
||||
|
||||
setMode -bscan
|
||||
setCable -p auto
|
||||
addDevice -p 1 -file build/projectname.bit
|
||||
program -p 1
|
||||
quit
|
||||
|
||||
- `digilent`
|
||||
|
||||
Uses the Digilent JTAG utility for programming, which must be installed
|
||||
separately. The name of the board must be set as `DJTG_DEVICE`; the
|
||||
path to the djtgcfg executable can be set as `DJTG_EXE`, and the index
|
||||
of the device can be set as `DJTG_INDEX`. You can set the flash index
|
||||
with `DJTG_FLASH_INDEX`.
|
||||
|
||||
- `xc3sprog`
|
||||
|
||||
Uses the xc3sprog utility for programming, which must also be installed
|
||||
separately. The cable name must be set as `XC3SPROG_CABLE`; additional
|
||||
options can be set as `XC3SPROG_OPTS`.
|
||||
|
||||
- `PROGRAMMER_PRE`
|
||||
|
||||
A command to be run before programming. This can be used to use `sudo` or
|
||||
`yes` to confirm programming.
|
||||
|
||||
## Targets
|
||||
|
||||
The Xilinx ISE Makefile implements the following targets:
|
||||
|
||||
- `make default` (or just `make`)
|
||||
|
||||
Builds the bitstream.
|
||||
|
||||
- `make clean`
|
||||
|
||||
Removes the build directory.
|
||||
|
||||
- `make prog`
|
||||
|
||||
Writes the bitstream to a target device. Requires some additional
|
||||
configuration; see below for details.
|
||||
|
||||
- `make flash`
|
||||
|
||||
Writes the bitstream to a flash device.
|
||||
**This is currently only for digilent implemented.**
|
||||
|
||||
## Console output
|
||||
|
||||
After a successful build, you will find the paths to the generated **reports** on the console. E.g.:
|
||||
|
||||
```
|
||||
============ Reports.. ===========
|
||||
|
||||
==== Synthesis Summary Report ====
|
||||
./build/Example.srp
|
||||
|
||||
======= Map Summary Report =======
|
||||
./build/Example.map.mrp
|
||||
|
||||
======= PAR Summary Report =======
|
||||
./build/Example.par
|
||||
|
||||
===== Pinout Summary Report ======
|
||||
./build/Example_pad.txt
|
||||
|
||||
```
|
||||
|
||||
## Unimplemented features
|
||||
|
||||
The following features are not currently implemented. (Pull requests are
|
||||
encouraged!)
|
||||
|
||||
- Generation of SPI or other unusual programming files
|
||||
|
||||
- CPLD synthesis
|
||||
|
||||
- Synthesis tools other than XST
|
||||
|
||||
- Display and/or handling of warnings and errors from `build/_xmsgs`
|
||||
|
||||
- Running unit tests
|
||||
|
||||
- Anything else (open an issue?)
|
||||
|
||||
## License
|
||||
|
||||
To the extent possible under law, the author(s) have dedicated all copyright
|
||||
and related and neighboring rights to this software to the public domain
|
||||
worldwide. This software is distributed without any warranty.
|
||||
|
||||
See LICENSE.md for details.
|
||||
@@ -1,110 +0,0 @@
|
||||
## Main settings.. ##
|
||||
|
||||
# Project name
|
||||
# @remark The name of the project is used as default name for the top module and the ucf file
|
||||
PROJECT =
|
||||
|
||||
# Target device
|
||||
# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
|
||||
TARGET_PART =
|
||||
|
||||
# Path to the Xilinx ISE installation
|
||||
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
# Optional the name of the top module (default is the project name)
|
||||
# TOPLEVEL =
|
||||
|
||||
# Optional the path/name of the ucf file (default is the project name)
|
||||
# CONSTRAINTS =
|
||||
|
||||
# Optional a target to copy the bit file to (make copy)
|
||||
# COPY_TARGET_DIR =
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Source files settings.. ##
|
||||
# The source files to be compiled
|
||||
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
|
||||
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
|
||||
|
||||
|
||||
## Test files settings.. ##
|
||||
# The testbench files to be compiled
|
||||
# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
|
||||
# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
|
||||
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## ISE executable settings.. ##
|
||||
|
||||
# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
|
||||
# COMMON_OPTS =
|
||||
|
||||
# Options for the XST synthesizer
|
||||
# @example -register_balancing (yes|no)
|
||||
# @example -opt_mode (speed|area)
|
||||
# @example -opt_level (1|2)
|
||||
XST_OPTS =
|
||||
|
||||
# Options for the NGDBuild tool
|
||||
# NGDBUILD_OPTS =
|
||||
|
||||
# Options for the MAP tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -cm speed (speed optimization)
|
||||
# @example -ol high
|
||||
# @example -detail
|
||||
# @example -timing
|
||||
MAP_OPTS =
|
||||
|
||||
# Options for the PAR tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -ol high
|
||||
PAR_OPTS =
|
||||
|
||||
# Options for the BitGen tool
|
||||
# @example -g Compress (compress bitstream)
|
||||
# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
|
||||
# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
|
||||
BITGEN_OPTS = -g StartupClk:JtagClk
|
||||
|
||||
# Options for the Trace tool
|
||||
# TRACE_OPTS =
|
||||
|
||||
# Options for the Fuse tool
|
||||
# FUSE_OPTS =
|
||||
|
||||
# Options for the ISim simulator
|
||||
# @example -gui (start the simulator in GUI mode)
|
||||
# ISIM_OPTS =
|
||||
|
||||
# Options for the ISim batch file
|
||||
# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
|
||||
# ISIM_CMD =
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Programmer settings.. ##
|
||||
|
||||
# The programmer to use
|
||||
# @example impact | digilent | xc3sprog
|
||||
# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
|
||||
PROGRAMMER =
|
||||
|
||||
## Digilent JTAG cable settings
|
||||
|
||||
# @remark Use the `djtgcfg enum` command to list all available devices
|
||||
# DJTG_DEVICE = DOnbUsb
|
||||
|
||||
# The index of the JTAG device for the `prog` target
|
||||
# DJTG_INDEX = 0
|
||||
|
||||
# The index of the flash device for the `flash` target
|
||||
# DJTG_FLASH_INDEX = 1
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
Submodule libs/AXI-HS-MUX deleted from 4d02a72b17
Submodule libs/AXI-HS-Scheduler deleted from f98e7d56f4
344
project.cfg
344
project.cfg
@@ -1,344 +0,0 @@
|
||||
## Main settings.. ##
|
||||
|
||||
# Project name
|
||||
# @remark The name of the project is used as default name for the top module and the ucf file
|
||||
PROJECT = SpriteChannel
|
||||
|
||||
# Target device
|
||||
# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
|
||||
TARGET_PART = xc3s1200e-4-fg320
|
||||
|
||||
# Path to the Xilinx ISE installation
|
||||
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
# Optional the name of the top module (default is the project name)
|
||||
TOPLEVEL = SpriteChannel
|
||||
|
||||
# Optional the path/name of the ucf file (default is the project name)
|
||||
CONSTRAINTS = src/SpriteChannel.ucf
|
||||
|
||||
# Optional a target to copy the bit file to (make copy)
|
||||
# COPY_TARGET_DIR =
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Source files settings.. ##
|
||||
# The source files to be compiled
|
||||
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
|
||||
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
|
||||
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd
|
||||
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineController.vhd
|
||||
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineStage.vhd
|
||||
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineFilter.vhd
|
||||
# VHDSOURCE += libs/PriorityEncoders.vhd
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_2.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_4.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_8.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_16.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_32.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_64.vhdl
|
||||
# VHDSOURCE += libs/AXI-HS-MUX/AXI_HS_MUX.vhd
|
||||
VHDSOURCE += libs/OPCodes.vhd
|
||||
|
||||
VHDSOURCE += src/VerticalSpritePipeline.vhd
|
||||
VHDSOURCE += src/RegisterFile.vhd
|
||||
VHDSOURCE += src/OPDecoder.vhd
|
||||
VHDSOURCE += src/Rom.vhd
|
||||
VHDSOURCE += src/RomPackage.vhd
|
||||
VHDSOURCE += src/HorizontalSpritePipeline.vhd
|
||||
VHDSOURCE += src/SpriteChannel.vhd
|
||||
|
||||
|
||||
## Test files settings.. ##
|
||||
# The testbench files to be compiled
|
||||
# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
|
||||
# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
|
||||
|
||||
# VHDTEST += test/Scheduler_tb.vhd
|
||||
# VHDTEST += test/OPDecoder_tb.vhd
|
||||
# VHDTEST += test/YHitCheck_tb.vhd
|
||||
# VHDTEST += test/SpriteChannel_tb.vhd
|
||||
# VHDTEST += test/RegisterFile_tb.vhd
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## ISE executable settings.. ##
|
||||
|
||||
# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
|
||||
# COMMON_OPTS =
|
||||
|
||||
# Options for the XST synthesizer
|
||||
#### Synthese Options (XST) #####
|
||||
|
||||
# Optimization goal: prioritize speed or area.
|
||||
# Values: Speed | Area
|
||||
XST_OPTS += -opt_mode Speed
|
||||
|
||||
# Optimization level: more aggressive optimizations at level 2.
|
||||
# Values: 1 | 2
|
||||
XST_OPTS += -opt_level 2
|
||||
|
||||
# Use the new XST parser (recommended for modern designs).
|
||||
# Values: yes | no
|
||||
XST_OPTS += -use_new_parser yes
|
||||
|
||||
# Preserve design hierarchy or allow flattening for optimization.
|
||||
# Values: Yes | No | Soft
|
||||
XST_OPTS += -keep_hierarchy No
|
||||
|
||||
# Determines how hierarchy is preserved in the netlist.
|
||||
# Values: As_Optimized | Rebuilt
|
||||
XST_OPTS += -netlist_hierarchy As_Optimized
|
||||
|
||||
# Global optimization strategy for nets.
|
||||
# Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay
|
||||
XST_OPTS += -glob_opt AllClockNets
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Enable reading of IP cores.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -read_cores YES
|
||||
|
||||
# Do not write timing constraints into synthesis report.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -write_timing_constraints NO
|
||||
|
||||
# Analyze paths across different clock domains.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -cross_clock_analysis NO
|
||||
|
||||
# Character used to separate hierarchy levels in instance names.
|
||||
# Default: /
|
||||
XST_OPTS += -hierarchy_separator /
|
||||
|
||||
# Delimiters used for bus signals.
|
||||
# Values: <> | [] | () | {}
|
||||
XST_OPTS += -bus_delimiter <>
|
||||
|
||||
# Maintain original case of identifiers.
|
||||
# Values: Maintain | Upper | Lower
|
||||
XST_OPTS += -case Maintain
|
||||
|
||||
# Target maximum utilization ratio for slices.
|
||||
# Values: 1–100
|
||||
XST_OPTS += -slice_utilization_ratio 100
|
||||
|
||||
# Target maximum utilization ratio for BRAMs.
|
||||
# Values: 1–100
|
||||
XST_OPTS += -bram_utilization_ratio 100
|
||||
|
||||
# Use Verilog 2001 syntax features.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -verilog2001 YES
|
||||
|
||||
#### HDL Options ####
|
||||
|
||||
## FSM ##
|
||||
|
||||
# Extract FSMs (Finite State Machines) from HDL code.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -fsm_extract YES
|
||||
|
||||
# Encoding strategy for FSMs.
|
||||
# Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User
|
||||
XST_OPTS += -fsm_encoding Auto
|
||||
|
||||
# Add safe logic for undefined FSM states.
|
||||
# Values: Yes | No
|
||||
XST_OPTS += -safe_implementation No
|
||||
|
||||
# Structure used to implement FSMs.
|
||||
# Values: LUT | BRAM
|
||||
XST_OPTS += -fsm_style LUT
|
||||
|
||||
## RAM/ROM ##
|
||||
|
||||
# Extract RAM inference from HDL.
|
||||
# Values: Yes | No
|
||||
XST_OPTS += -ram_extract Yes
|
||||
|
||||
# Style used to implement RAM.
|
||||
# Values: Auto | Block | Distributed
|
||||
XST_OPTS += -ram_style Auto
|
||||
|
||||
# Extract ROM inference from HDL.
|
||||
# Values: Yes | No
|
||||
XST_OPTS += -rom_extract Yes
|
||||
|
||||
# Style used for implementing ROM.
|
||||
# Values: Auto | Distributed | Block
|
||||
XST_OPTS += -rom_style Auto
|
||||
|
||||
# Enable or disable automatic BRAM packing.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -auto_bram_packing NO
|
||||
|
||||
## MUX/Decoder/Shift Register ##
|
||||
|
||||
# Extract multiplexers where possible.
|
||||
# Values: Yes | No | Force
|
||||
XST_OPTS += -mux_extract Yes
|
||||
|
||||
# Style used for implementing MUX logic.
|
||||
# Values: Auto | MUXCY | MUXF
|
||||
XST_OPTS += -mux_style Auto
|
||||
|
||||
# Extract decoder logic from behavioral code.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -decoder_extract YES
|
||||
|
||||
# Extract and optimize priority encoder structures.
|
||||
# Values: Yes | No | Force
|
||||
XST_OPTS += -priority_extract Yes
|
||||
|
||||
# Extract shift register logic.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -shreg_extract YES
|
||||
|
||||
# Extract simple shift operations into dedicated hardware.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -shift_extract YES
|
||||
|
||||
## Multiplier ##
|
||||
|
||||
# Style for implementing multipliers.
|
||||
# Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block
|
||||
XST_OPTS += -mult_style Auto
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Collapse XOR trees where beneficial.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -xor_collapse YES
|
||||
|
||||
# Share resources like adders or multipliers between logic blocks.
|
||||
# Values: YES | NO | Force
|
||||
XST_OPTS += -resource_sharing YES
|
||||
|
||||
# Convert asynchronous resets to synchronous where possible.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -async_to_sync NO
|
||||
|
||||
#### Xilinx Specific Options ####
|
||||
|
||||
## Optimization ##
|
||||
|
||||
# Enable removal of logically equivalent registers.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -equivalent_register_removal YES
|
||||
|
||||
# Duplicate registers to reduce fanout or improve timing.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -register_duplication YES
|
||||
|
||||
# Move registers across logic to balance timing.
|
||||
# Values: Yes | No | Forward | Backward
|
||||
XST_OPTS += -register_balancing No
|
||||
|
||||
# Use clock enable signals where possible.
|
||||
# Values: Auto | Yes | No
|
||||
XST_OPTS += -use_clock_enable Yes
|
||||
|
||||
# Use synchronous set (preset) signals when available.
|
||||
# Values: Auto | Yes | No
|
||||
XST_OPTS += -use_sync_set Yes
|
||||
|
||||
# Use synchronous reset signals where possible.
|
||||
# Values: Auto | Yes | No
|
||||
XST_OPTS += -use_sync_reset Yes
|
||||
|
||||
## I/O ##
|
||||
|
||||
# Insert IO buffers for top-level ports.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -iobuf YES
|
||||
|
||||
# Placement strategy for IOB registers (Auto = let tools decide).
|
||||
# Values: Auto | YES | NO
|
||||
XST_OPTS += -iob Auto
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Maximum allowed fanout for a net.
|
||||
# Values: integer (e.g., 500)
|
||||
XST_OPTS += -max_fanout 500
|
||||
|
||||
# Maximum number of BUFGs (global buffers) to use.
|
||||
# Values: 0–32 (device-dependent)
|
||||
XST_OPTS += -bufg 24
|
||||
|
||||
# Enable logic packing into slices.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -slice_packing YES
|
||||
|
||||
# Try to reduce the number of primitive instances used.
|
||||
# Values: YES | NO
|
||||
XST_OPTS += -optimize_primitives NO
|
||||
|
||||
# Margin in percent beyond the target slice utilization.
|
||||
# Values: 0–100
|
||||
XST_OPTS += -slice_utilization_ratio_maxmargin 5
|
||||
|
||||
|
||||
# Options for the NGDBuild tool
|
||||
# NGDBUILD_OPTS =
|
||||
|
||||
# Options for the MAP tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -cm speed (speed optimization)
|
||||
# @example -ol high
|
||||
# @example -detail
|
||||
# @example -timing
|
||||
MAP_OPTS = -detail -timing -ol high
|
||||
|
||||
# Options for the PAR tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -ol high
|
||||
PAR_OPTS = -ol high
|
||||
|
||||
# Options for the BitGen tool
|
||||
# @example -g Compress (compress bitstream)
|
||||
# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
|
||||
# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
|
||||
BITGEN_OPTS = -g StartupClk:JtagClk
|
||||
|
||||
# Options for the Trace tool
|
||||
# TRACE_OPTS =
|
||||
|
||||
# Options for the Fuse tool
|
||||
# FUSE_OPTS =
|
||||
|
||||
# Options for the ISim simulator
|
||||
# @example -gui (start the simulator in GUI mode)
|
||||
# ISIM_OPTS =
|
||||
|
||||
# Options for the ISim batch file
|
||||
# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit
|
||||
# ISIM_CMD = vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Programmer settings.. ##
|
||||
|
||||
# The programmer to use
|
||||
# @example impact | digilent | xc3sprog
|
||||
# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
|
||||
PROGRAMMER =
|
||||
|
||||
## Digilent JTAG cable settings
|
||||
|
||||
# @remark Use the `djtgcfg enum` command to list all available devices
|
||||
# DJTG_DEVICE = DOnbUsb
|
||||
|
||||
# The index of the JTAG device for the `prog` target
|
||||
# DJTG_INDEX = 0
|
||||
|
||||
# The index of the flash device for the `flash` target
|
||||
# DJTG_FLASH_INDEX = 1
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
270
project.yml
Normal file
270
project.yml
Normal file
@@ -0,0 +1,270 @@
|
||||
name: SpriteChannel
|
||||
topmodule: SpriteChannel
|
||||
target_device: xc3s1200e-4-fg320
|
||||
xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
constraints: src/SpriteChannel.ucf
|
||||
|
||||
sources:
|
||||
vhdl:
|
||||
- path: src/*.vhd
|
||||
library: work
|
||||
- path: libs/*.vhd
|
||||
library: work
|
||||
|
||||
testbenches:
|
||||
vhdl:
|
||||
- path: tests/*.vhd
|
||||
library: work
|
||||
|
||||
dependencies:
|
||||
- git: "https://git.0xmax42.io/HDL/Pipeline-AXI-Handshake.git"
|
||||
rev: "main"
|
||||
|
||||
build:
|
||||
build_dir: working
|
||||
report_dir: reports
|
||||
copy_target_dir: output
|
||||
|
||||
# Tool Optionen
|
||||
tool_options:
|
||||
common:
|
||||
- "-intstyle"
|
||||
- "xflow"
|
||||
|
||||
ngdbuild: []
|
||||
|
||||
map:
|
||||
- "-detail"
|
||||
- "-timing"
|
||||
- "-ol"
|
||||
- "high"
|
||||
|
||||
par: []
|
||||
|
||||
bitgen:
|
||||
- "-g"
|
||||
- "StartupClk:JtagClk"
|
||||
|
||||
trace:
|
||||
- "-v"
|
||||
- "3"
|
||||
- "-n"
|
||||
- "3"
|
||||
|
||||
fuse:
|
||||
- "-incremental"
|
||||
|
||||
isim:
|
||||
- "-gui"
|
||||
|
||||
xst:
|
||||
# Optimization goal: prioritize speed or area.
|
||||
# Values: Speed | Area
|
||||
- "-opt_mode Speed"
|
||||
|
||||
# Optimization level: more aggressive optimizations at level 2.
|
||||
# Values: 1 | 2
|
||||
- "-opt_level 2"
|
||||
|
||||
# Use the new XST parser (recommended for modern designs).
|
||||
# Values: yes | no
|
||||
- "-use_new_parser yes"
|
||||
|
||||
# Preserve design hierarchy or allow flattening for optimization.
|
||||
# Values: Yes | No | Soft
|
||||
- "-keep_hierarchy No"
|
||||
|
||||
# Determines how hierarchy is preserved in the netlist.
|
||||
# Values: As_Optimized | Rebuilt
|
||||
- "-netlist_hierarchy As_Optimized"
|
||||
|
||||
# Global optimization strategy for nets.
|
||||
# Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay
|
||||
- "-glob_opt AllClockNets"
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Enable reading of IP cores.
|
||||
# Values: YES | NO
|
||||
- "-read_cores YES"
|
||||
|
||||
# Do not write timing constraints into synthesis report.
|
||||
# Values: YES | NO
|
||||
- "-write_timing_constraints NO"
|
||||
|
||||
# Analyze paths across different clock domains.
|
||||
# Values: YES | NO
|
||||
- "-cross_clock_analysis NO"
|
||||
|
||||
# Character used to separate hierarchy levels in instance names.
|
||||
# Default: /
|
||||
- "-hierarchy_separator /"
|
||||
|
||||
# Delimiters used for bus signals.
|
||||
# Values: <> | [] | () | {}
|
||||
- "-bus_delimiter <>"
|
||||
|
||||
# Maintain original case of identifiers.
|
||||
# Values: Maintain | Upper | Lower
|
||||
- "-case Maintain"
|
||||
|
||||
# Target maximum utilization ratio for slices.
|
||||
# Values: 1–100
|
||||
- "-slice_utilization_ratio 100"
|
||||
|
||||
# Target maximum utilization ratio for BRAMs.
|
||||
# Values: 1–100
|
||||
- "-bram_utilization_ratio 100"
|
||||
|
||||
# Use Verilog 2001 syntax features.
|
||||
# Values: YES | NO
|
||||
- "-verilog2001 YES"
|
||||
|
||||
#### HDL Options ####
|
||||
|
||||
## FSM ##
|
||||
|
||||
# Extract FSMs (Finite State Machines) from HDL code.
|
||||
# Values: YES | NO
|
||||
- "-fsm_extract YES"
|
||||
|
||||
# Encoding strategy for FSMs.
|
||||
# Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User
|
||||
- "-fsm_encoding Auto"
|
||||
|
||||
# Add safe logic for undefined FSM states.
|
||||
# Values: Yes | No
|
||||
- "-safe_implementation No"
|
||||
|
||||
# Structure used to implement FSMs.
|
||||
# Values: LUT | BRAM
|
||||
- "-fsm_style LUT"
|
||||
|
||||
## RAM/ROM ##
|
||||
|
||||
# Extract RAM inference from HDL.
|
||||
# Values: Yes | No
|
||||
- "-ram_extract Yes"
|
||||
|
||||
# Style used to implement RAM.
|
||||
# Values: Auto | Block | Distributed
|
||||
- "-ram_style Auto"
|
||||
|
||||
# Extract ROM inference from HDL.
|
||||
# Values: Yes | No
|
||||
- "-rom_extract Yes"
|
||||
|
||||
# Style used for implementing ROM.
|
||||
# Values: Auto | Distributed | Block
|
||||
- "-rom_style Auto"
|
||||
|
||||
# Enable or disable automatic BRAM packing.
|
||||
# Values: YES | NO
|
||||
- "-auto_bram_packing NO"
|
||||
|
||||
## MUX/Decoder/Shift Register ##
|
||||
|
||||
# Extract multiplexers where possible.
|
||||
# Values: Yes | No | Force
|
||||
- "-mux_extract Yes"
|
||||
|
||||
# Style used for implementing MUX logic.
|
||||
# Values: Auto | MUXCY | MUXF
|
||||
- "-mux_style Auto"
|
||||
|
||||
# Extract decoder logic from behavioral code.
|
||||
# Values: YES | NO
|
||||
- "-decoder_extract YES"
|
||||
|
||||
# Extract and optimize priority encoder structures.
|
||||
# Values: Yes | No | Force
|
||||
- "-priority_extract Yes"
|
||||
|
||||
# Extract shift register logic.
|
||||
# Values: YES | NO
|
||||
- "-shreg_extract YES"
|
||||
|
||||
# Extract simple shift operations into dedicated hardware.
|
||||
# Values: YES | NO
|
||||
- "-shift_extract YES"
|
||||
|
||||
## Multiplier ##
|
||||
|
||||
# Style for implementing multipliers.
|
||||
# Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block
|
||||
- "-mult_style Auto"
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Collapse XOR trees where beneficial.
|
||||
# Values: YES | NO
|
||||
- "-xor_collapse YES"
|
||||
|
||||
# Share resources like adders or multipliers between logic blocks.
|
||||
# Values: YES | NO | Force
|
||||
- "-resource_sharing YES"
|
||||
|
||||
# Convert asynchronous resets to synchronous where possible.
|
||||
# Values: YES | NO
|
||||
- "-async_to_sync NO"
|
||||
|
||||
#### Xilinx Specific Options ####
|
||||
|
||||
## Optimization ##
|
||||
|
||||
# Enable removal of logically equivalent registers.
|
||||
# Values: YES | NO
|
||||
- "-equivalent_register_removal YES"
|
||||
|
||||
# Duplicate registers to reduce fanout or improve timing.
|
||||
# Values: YES | NO
|
||||
- "-register_duplication YES"
|
||||
|
||||
# Move registers across logic to balance timing.
|
||||
# Values: Yes | No | Forward | Backward
|
||||
- "-register_balancing No"
|
||||
|
||||
# Use clock enable signals where possible.
|
||||
# Values: Auto | Yes | No
|
||||
- "-use_clock_enable Yes"
|
||||
|
||||
# Use synchronous set (preset) signals when available.
|
||||
# Values: Auto | Yes | No
|
||||
- "-use_sync_set Yes"
|
||||
|
||||
# Use synchronous reset signals where possible.
|
||||
# Values: Auto | Yes | No
|
||||
- "-use_sync_reset Yes"
|
||||
|
||||
## I/O ##
|
||||
|
||||
# Insert IO buffers for top-level ports.
|
||||
# Values: YES | NO
|
||||
- "-iobuf YES"
|
||||
|
||||
# Placement strategy for IOB registers (Auto = let tools decide).
|
||||
# Values: Auto | YES | NO
|
||||
- "-iob Auto"
|
||||
|
||||
## Misc ##
|
||||
|
||||
# Maximum allowed fanout for a net.
|
||||
# Values: integer (e.g., 500)
|
||||
- "-max_fanout 500"
|
||||
|
||||
# Maximum number of BUFGs (global buffers) to use.
|
||||
# Values: 0–32 (device-dependent)
|
||||
- "-bufg 24"
|
||||
|
||||
# Enable logic packing into slices.
|
||||
# Values: YES | NO
|
||||
- "-slice_packing YES"
|
||||
|
||||
# Try to reduce the number of primitive instances used.
|
||||
# Values: YES | NO
|
||||
- "-optimize_primitives NO"
|
||||
|
||||
# Margin in percent beyond the target slice utilization.
|
||||
# Values: 0–100
|
||||
- "-slice_utilization_ratio_maxmargin 5"
|
||||
@@ -82,7 +82,8 @@ begin
|
||||
|
||||
INST0_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Y_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Y_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -93,7 +94,8 @@ begin
|
||||
|
||||
INST0_VSpritePipeline_Y_Request : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Y_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Y_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -109,7 +111,8 @@ begin
|
||||
|
||||
INST_VSpritePipeline_Y_Bottom_Sprite : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Y_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Y_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -120,7 +123,8 @@ begin
|
||||
|
||||
INST1_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Y_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Y_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -131,7 +135,8 @@ begin
|
||||
|
||||
INST1_VSpritePipeline_Y_Request : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Y_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Y_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -147,15 +152,26 @@ begin
|
||||
) else '0';
|
||||
|
||||
--@ Calculate the offset address of the sprite
|
||||
C_Offset <= std_logic_vector(
|
||||
to_unsigned(
|
||||
K_SPRITE_ROW_OFFSETS(to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite))),
|
||||
C_Offset'length)
|
||||
);
|
||||
process (R1_Y_Request, R1_Y_Sprite)
|
||||
variable V_SPRITE_ROW_OFFSETS_Address : integer := 0;
|
||||
begin
|
||||
V_SPRITE_ROW_OFFSETS_Address := to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite));
|
||||
|
||||
if V_SPRITE_ROW_OFFSETS_Address > 0 and V_SPRITE_ROW_OFFSETS_Address < G_Sprite_Height then
|
||||
C_Offset <= std_logic_vector(
|
||||
to_unsigned(
|
||||
K_SPRITE_ROW_OFFSETS(V_SPRITE_ROW_OFFSETS_Address),
|
||||
C_Offset'length)
|
||||
);
|
||||
else
|
||||
C_Offset <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
INST_IsVisible_OutputRegister : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => 1
|
||||
G_PipelineStages => 1,
|
||||
G_Width => 1
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
@@ -166,7 +182,8 @@ begin
|
||||
|
||||
INST_Offset_OutputRegister : entity work.PipelineRegister
|
||||
generic map(
|
||||
G_Width => G_Offset_Width
|
||||
G_PipelineStages => 1,
|
||||
G_Width => G_Offset_Width
|
||||
)
|
||||
port map(
|
||||
I_CLK => I_CLK,
|
||||
|
||||
Reference in New Issue
Block a user