Remove obsolete build files including .gitignore, LICENSE.md, Makefile, README.md, and project.cfg.sample
This commit is contained in:
2
build/.gitignore
vendored
2
build/.gitignore
vendored
@@ -1,2 +0,0 @@
|
||||
working/
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||||
reports/
|
||||
@@ -1,24 +0,0 @@
|
||||
This is free and unencumbered software released into the public domain.
|
||||
|
||||
Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
distribute this software, either in source code form or as a compiled
|
||||
binary, for any purpose, commercial or non-commercial, and by any
|
||||
means.
|
||||
|
||||
In jurisdictions that recognize copyright laws, the author or authors
|
||||
of this software dedicate any and all copyright interest in the
|
||||
software to the public domain. We make this dedication for the benefit
|
||||
of the public at large and to the detriment of our heirs and
|
||||
successors. We intend this dedication to be an overt act of
|
||||
relinquishment in perpetuity of all present and future rights to this
|
||||
software under copyright law.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
For more information, please refer to <http://unlicense.org>
|
||||
275
build/Makefile
275
build/Makefile
@@ -1,275 +0,0 @@
|
||||
###########################################################################
|
||||
## Xilinx ISE Makefile
|
||||
##
|
||||
## To the extent possible under law, the author(s) have dedicated all copyright
|
||||
## and related and neighboring rights to this software to the public domain
|
||||
## worldwide. This software is distributed without any warranty.
|
||||
##
|
||||
## Makefile github repository: https://github.com/PxaMMaxP/Xilinx-ISE-Makefile
|
||||
###########################################################################
|
||||
|
||||
###########################################################################
|
||||
# Version
|
||||
###########################################################################
|
||||
|
||||
Makefile_Version := 1.1.5
|
||||
$(info ISE Makefile Version: $(Makefile_Version))
|
||||
|
||||
###########################################################################
|
||||
# Include project configuration
|
||||
###########################################################################
|
||||
|
||||
include ../project.cfg
|
||||
|
||||
###########################################################################
|
||||
# Default values
|
||||
###########################################################################
|
||||
|
||||
ifndef XILINX
|
||||
$(error XILINX must be defined)
|
||||
endif
|
||||
|
||||
ifndef PROJECT
|
||||
$(error PROJECT must be defined)
|
||||
endif
|
||||
|
||||
ifndef TARGET_PART
|
||||
$(error TARGET_PART must be defined)
|
||||
endif
|
||||
|
||||
TOPLEVEL ?= $(PROJECT)
|
||||
CONSTRAINTS ?= $(PROJECT).ucf
|
||||
BUILD_DIR ?= working
|
||||
REPORT_DIR ?= reports
|
||||
BITFILE ?= $(BUILD_DIR)/$(PROJECT).bit
|
||||
|
||||
COMMON_OPTS ?= -intstyle xflow
|
||||
XST_OPTS ?=
|
||||
NGDBUILD_OPTS ?=
|
||||
MAP_OPTS ?= -detail
|
||||
PAR_OPTS ?=
|
||||
BITGEN_OPTS ?=
|
||||
TRACE_OPTS ?= -v 3 -n 3
|
||||
FUSE_OPTS ?= -incremental
|
||||
|
||||
ISIM_OPTS ?= -gui
|
||||
ISIM_CMD ?=
|
||||
|
||||
PROGRAMMER ?= none
|
||||
PROGRAMMER_PRE ?=
|
||||
|
||||
IMPACT_OPTS ?= -batch impact.cmd
|
||||
|
||||
DJTG_EXE ?= djtgcfg
|
||||
DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
|
||||
DJTG_INDEX ?= 0
|
||||
DJTG_FLASH_INDEX ?= 1
|
||||
|
||||
XC3SPROG_EXE ?= xc3sprog
|
||||
XC3SPROG_CABLE ?= none
|
||||
XC3SPROG_OPTS ?=
|
||||
|
||||
|
||||
###########################################################################
|
||||
# Internal variables, platform-specific definitions, and macros
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
XILINX := $(shell cygpath -m $(XILINX))
|
||||
CYG_XILINX := $(shell cygpath $(XILINX))
|
||||
EXE := .exe
|
||||
XILINX_PLATFORM ?= nt64
|
||||
PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
|
||||
else
|
||||
EXE :=
|
||||
XILINX_PLATFORM ?= lin64
|
||||
PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
|
||||
endif
|
||||
|
||||
TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
|
||||
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
|
||||
|
||||
RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
|
||||
cd $(BUILD_DIR) && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
|
||||
|
||||
# isim executables don't work without this
|
||||
export XILINX
|
||||
|
||||
# Initialize the libs and paths variables for VHDL and Verilog sources
|
||||
VHD_PATHS ?=
|
||||
VHD_LIBS ?=
|
||||
V_PATHS ?=
|
||||
V_LIBS ?=
|
||||
|
||||
# Define a function to process source files
|
||||
define process_sources
|
||||
$(foreach src,$(1),\
|
||||
$(eval lib_and_path=$(subst :, ,$(src))) \
|
||||
$(eval libname=$(word 1,$(lib_and_path))) \
|
||||
$(eval filepath=$(word 2,$(lib_and_path))) \
|
||||
$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
|
||||
$(eval $(2) += $(libname)) \
|
||||
$(eval $(3) += ../$(filepath)) \
|
||||
)
|
||||
endef
|
||||
|
||||
# Run the function for VHDL sources
|
||||
$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
|
||||
# Run the function for Verilog sources
|
||||
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
|
||||
|
||||
## Tests
|
||||
|
||||
# Initialize the libs and paths variables for VHDL and Verilog testbenches
|
||||
VHD_TEST_PATHS ?=
|
||||
VHD_TEST_LIBS ?=
|
||||
V_TEST_PATHS ?=
|
||||
V_TEST_LIBS ?=
|
||||
|
||||
# Run the function for VHDL tests
|
||||
$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
|
||||
# Run the function for Verilog tests
|
||||
$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
|
||||
|
||||
# Get the test names..
|
||||
TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
|
||||
TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
|
||||
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
|
||||
|
||||
###########################################################################
|
||||
# Default build
|
||||
###########################################################################
|
||||
|
||||
default: $(BITFILE)
|
||||
|
||||
clean:
|
||||
rm -rf $(BUILD_DIR)
|
||||
rm -rf $(REPORT_DIR)
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
|
||||
@echo "Updating $@"
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@mkdir -p $(REPORT_DIR)
|
||||
@rm -f $@
|
||||
@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
|
||||
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
|
||||
@cp $(BUILD_DIR)/$(PROJECT).prj $@
|
||||
@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
|
||||
@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
|
||||
|
||||
$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
|
||||
@echo "Updating $@"
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@rm -f $@
|
||||
@echo "run" \
|
||||
"-ifn $(PROJECT).prj" \
|
||||
"-ofn $(PROJECT).ngc" \
|
||||
"-ifmt mixed" \
|
||||
"$(XST_OPTS)" \
|
||||
"-top $(TOPLEVEL)" \
|
||||
"-ofmt NGC" \
|
||||
"-p $(TARGET_PART)" \
|
||||
> $(BUILD_DIR)/$(PROJECT).scr
|
||||
|
||||
$(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR)/$(PROJECT).prj $(BUILD_DIR)/$(PROJECT).scr
|
||||
@mkdir -p $(BUILD_DIR)
|
||||
@mkdir -p $(REPORT_DIR)
|
||||
$(call RUN,xst) $(COMMON_OPTS) \
|
||||
-ifn $(PROJECT).scr
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).srp $(REPORT_DIR)/$(PROJECT).SynthesisReport
|
||||
$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
|
||||
-p $(TARGET_PART) -uc ../../$(CONSTRAINTS) \
|
||||
$(PROJECT).ngc $(PROJECT).ngd
|
||||
$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
|
||||
-p $(TARGET_PART) \
|
||||
-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).map.mrp $(REPORT_DIR)/$(PROJECT).MapReport
|
||||
$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
|
||||
-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).par $(REPORT_DIR)/$(PROJECT).PlaceRouteReport
|
||||
$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
|
||||
-w $(PROJECT).ncd $(PROJECT).bit
|
||||
@echo "\e[1;32m============ OK ============\e[m\n\n"
|
||||
@echo "\e[1;33m============ Reports.. ===========\e[m\n"
|
||||
@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).SynthesisReport\e[m\n"
|
||||
@echo "\e[1;97m======= Map Summary Report =======\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).MapReport\e[m\n"
|
||||
@echo "\e[1;97m======= PAR Summary Report =======\e[m"
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PlaceRouteReport\e[m\n"
|
||||
@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT)_pad.txt $(REPORT_DIR)/$(PROJECT).PinoutReport
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).PinoutReport\e[m\n"
|
||||
|
||||
copy: $(BITFILE)
|
||||
@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
|
||||
@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
|
||||
|
||||
###########################################################################
|
||||
# Testing (work in progress)
|
||||
###########################################################################
|
||||
|
||||
trace: ../project.cfg $(BITFILE)
|
||||
$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
|
||||
$(PROJECT).ncd $(PROJECT).pcf
|
||||
@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
|
||||
@echo "\e[1;97m===== Timing Summary Report ======\e[m"
|
||||
@cp ./$(BUILD_DIR)/$(PROJECT).twr $(REPORT_DIR)/$(PROJECT).TimingReport
|
||||
@echo "\e[1;35m ./$(REPORT_DIR)/$(PROJECT).TimingReport\e[m\n"
|
||||
|
||||
test: buildtest runtest
|
||||
|
||||
runtest: ${TEST_NAMES}
|
||||
|
||||
${TEST_NAMES}:
|
||||
@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
|
||||
@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
|
||||
cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
|
||||
|
||||
buildtest: ${TEST_EXES}
|
||||
|
||||
$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
|
||||
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
|
||||
-prj $(PROJECT)_sim.prj \
|
||||
-o isim_$*$(EXE) \
|
||||
work.$* work.glbl
|
||||
|
||||
|
||||
###########################################################################
|
||||
# Programming
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(PROGRAMMER), impact)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), xc3sprog)
|
||||
prog: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), none)
|
||||
prog:
|
||||
$(error PROGRAMMER must be set to use 'make prog')
|
||||
endif
|
||||
|
||||
###########################################################################
|
||||
# Flash
|
||||
###########################################################################
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
flash: $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
###########################################################################
|
||||
225
build/README.md
225
build/README.md
@@ -1,225 +0,0 @@
|
||||
# Xilinx ISE Makefile
|
||||
|
||||
Tired of clicking around in Xilinx ISE? Run your builds from the command line!
|
||||
|
||||
## Forked from..
|
||||
|
||||
The original project is located at [Xilinx-ISE-Makefile](https://github.com/duskwuff/Xilinx-ISE-Makefile) and was created by [duskwuff](github.com/duskwuff/).
|
||||
|
||||
Many thanks for the good work!
|
||||
|
||||
## Requirements
|
||||
|
||||
- Xilinx ISE, ideally 14.7 (the final version)
|
||||
|
||||
Works great on Linux. Windows Subsystem for Linux is tested and works well.
|
||||
|
||||
- GNU (or compatible?) Make
|
||||
|
||||
Install this through Cygwin on Windows.
|
||||
|
||||
## Creating a project
|
||||
|
||||
To start building a project, you will need to create a file `project.cfg` in
|
||||
the top level of your project. This file is a text file sourced by Make, so
|
||||
it consists of `KEY = value` pairs. It must define at least the following keys:
|
||||
|
||||
- `PROJECT`
|
||||
|
||||
The name of the project, used as a name for certain intermediate files, and
|
||||
as the default name for the top-level module and constraints file.
|
||||
|
||||
- `TARGET_PART`
|
||||
|
||||
The full part-speed-package identifier for the Xilinx part to be targeted,
|
||||
e.g. `xc6slx9-2-tqg144`.
|
||||
|
||||
- `XILINX`
|
||||
|
||||
The path to the appropriate binaries directory of the target Xilinx ISE
|
||||
install, e.g.
|
||||
`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE`
|
||||
or
|
||||
`/opt/Xilinx/14.7/ISE_DS/ISE`
|
||||
for typical installs.
|
||||
|
||||
- `VSOURCE` and/or `VHDSOURCE`
|
||||
|
||||
The space-separated names of all Verilog and/or VHDL source files to be
|
||||
used in the project.
|
||||
|
||||
You can define these on multiple lines using `+=`, e.g.
|
||||
|
||||
VSOURCE += foo.v
|
||||
VSOURCE += bar.v
|
||||
|
||||
You can also add a library name to the source file, e.g.
|
||||
|
||||
VSOURCE += my_lib:foo.v
|
||||
VSOURCE += my_lib:bar.v
|
||||
|
||||
The default library name is `work`.
|
||||
|
||||
A simple `project.cfg` may thus resemble:
|
||||
|
||||
PROJECT = example
|
||||
TARGET_PART = xc6slx9-2-cpg196
|
||||
|
||||
XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
|
||||
|
||||
VSOURCE = example.v
|
||||
|
||||
A number of other keys can be set in the project configuration, including:
|
||||
|
||||
- `XILINX_PLATFORM`
|
||||
|
||||
The Xilinx name for the platform to build for, e.g. `nt64` or `lin`.
|
||||
`nt64` is used by default for Windows systems, and `lin64` for Linux
|
||||
systems, so you only need to set this if you explicitly need to use the
|
||||
32-bit version of the tools for some reason.
|
||||
|
||||
- `TOPLEVEL`
|
||||
|
||||
The name of the top-level module to be used in the project.
|
||||
(Defaults to `$PROJECT`.)
|
||||
|
||||
- `CONSTRAINTS`
|
||||
|
||||
The name of the constraints file (`.ucf`) to be used for the project.
|
||||
(Defaults to `$PROJECT.ucf`.)
|
||||
|
||||
- `COMMON_OPTS`
|
||||
|
||||
Extra command-line options to be passed to all ISE executables. Defaults to
|
||||
`-intstyle xflow`.
|
||||
|
||||
- `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,
|
||||
`TRACE_OPTS`, `FUSE_OPTS`
|
||||
|
||||
Extra command-line options to be passed to the corresponding ISE tools.
|
||||
|
||||
Defaults is:
|
||||
|
||||
```
|
||||
XST_OPTS ?=
|
||||
NGDBUILD_OPTS ?=
|
||||
MAP_OPTS ?= -detail
|
||||
PAR_OPTS ?=
|
||||
BITGEN_OPTS ?=
|
||||
TRACE_OPTS ?= -v 3 -n 3
|
||||
FUSE_OPTS ?= -incremental
|
||||
```
|
||||
|
||||
Note that `XST_OPTS` will not appear on the command line during
|
||||
compilation, as the XST options are embedded in a script file.
|
||||
|
||||
`MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading,
|
||||
which may speed up compilation of large designs.
|
||||
|
||||
`BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression.
|
||||
|
||||
- `PROGRAMMER`
|
||||
|
||||
The name of the programmer to be used for `make prog`. Currently supported
|
||||
values are:
|
||||
|
||||
- `impact`
|
||||
|
||||
Uses Xilinx iMPACT for programming, using a batch file named
|
||||
`impact.cmd` by default. The iMPACT command line may be overridden by
|
||||
setting `IMPACT_OPTS`.
|
||||
|
||||
A typical batch file may resemble:
|
||||
|
||||
setMode -bscan
|
||||
setCable -p auto
|
||||
addDevice -p 1 -file build/projectname.bit
|
||||
program -p 1
|
||||
quit
|
||||
|
||||
- `digilent`
|
||||
|
||||
Uses the Digilent JTAG utility for programming, which must be installed
|
||||
separately. The name of the board must be set as `DJTG_DEVICE`; the
|
||||
path to the djtgcfg executable can be set as `DJTG_EXE`, and the index
|
||||
of the device can be set as `DJTG_INDEX`. You can set the flash index
|
||||
with `DJTG_FLASH_INDEX`.
|
||||
|
||||
- `xc3sprog`
|
||||
|
||||
Uses the xc3sprog utility for programming, which must also be installed
|
||||
separately. The cable name must be set as `XC3SPROG_CABLE`; additional
|
||||
options can be set as `XC3SPROG_OPTS`.
|
||||
|
||||
- `PROGRAMMER_PRE`
|
||||
|
||||
A command to be run before programming. This can be used to use `sudo` or
|
||||
`yes` to confirm programming.
|
||||
|
||||
## Targets
|
||||
|
||||
The Xilinx ISE Makefile implements the following targets:
|
||||
|
||||
- `make default` (or just `make`)
|
||||
|
||||
Builds the bitstream.
|
||||
|
||||
- `make clean`
|
||||
|
||||
Removes the build directory.
|
||||
|
||||
- `make prog`
|
||||
|
||||
Writes the bitstream to a target device. Requires some additional
|
||||
configuration; see below for details.
|
||||
|
||||
- `make flash`
|
||||
|
||||
Writes the bitstream to a flash device.
|
||||
**This is currently only for digilent implemented.**
|
||||
|
||||
## Console output
|
||||
|
||||
After a successful build, you will find the paths to the generated **reports** on the console. E.g.:
|
||||
|
||||
```
|
||||
============ Reports.. ===========
|
||||
|
||||
==== Synthesis Summary Report ====
|
||||
./build/Example.srp
|
||||
|
||||
======= Map Summary Report =======
|
||||
./build/Example.map.mrp
|
||||
|
||||
======= PAR Summary Report =======
|
||||
./build/Example.par
|
||||
|
||||
===== Pinout Summary Report ======
|
||||
./build/Example_pad.txt
|
||||
|
||||
```
|
||||
|
||||
## Unimplemented features
|
||||
|
||||
The following features are not currently implemented. (Pull requests are
|
||||
encouraged!)
|
||||
|
||||
- Generation of SPI or other unusual programming files
|
||||
|
||||
- CPLD synthesis
|
||||
|
||||
- Synthesis tools other than XST
|
||||
|
||||
- Display and/or handling of warnings and errors from `build/_xmsgs`
|
||||
|
||||
- Running unit tests
|
||||
|
||||
- Anything else (open an issue?)
|
||||
|
||||
## License
|
||||
|
||||
To the extent possible under law, the author(s) have dedicated all copyright
|
||||
and related and neighboring rights to this software to the public domain
|
||||
worldwide. This software is distributed without any warranty.
|
||||
|
||||
See LICENSE.md for details.
|
||||
@@ -1,110 +0,0 @@
|
||||
## Main settings.. ##
|
||||
|
||||
# Project name
|
||||
# @remark The name of the project is used as default name for the top module and the ucf file
|
||||
PROJECT =
|
||||
|
||||
# Target device
|
||||
# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
|
||||
TARGET_PART =
|
||||
|
||||
# Path to the Xilinx ISE installation
|
||||
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
# Optional the name of the top module (default is the project name)
|
||||
# TOPLEVEL =
|
||||
|
||||
# Optional the path/name of the ucf file (default is the project name)
|
||||
# CONSTRAINTS =
|
||||
|
||||
# Optional a target to copy the bit file to (make copy)
|
||||
# COPY_TARGET_DIR =
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Source files settings.. ##
|
||||
# The source files to be compiled
|
||||
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
|
||||
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
|
||||
|
||||
|
||||
## Test files settings.. ##
|
||||
# The testbench files to be compiled
|
||||
# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
|
||||
# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
|
||||
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## ISE executable settings.. ##
|
||||
|
||||
# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
|
||||
# COMMON_OPTS =
|
||||
|
||||
# Options for the XST synthesizer
|
||||
# @example -register_balancing (yes|no)
|
||||
# @example -opt_mode (speed|area)
|
||||
# @example -opt_level (1|2)
|
||||
XST_OPTS =
|
||||
|
||||
# Options for the NGDBuild tool
|
||||
# NGDBUILD_OPTS =
|
||||
|
||||
# Options for the MAP tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -cm speed (speed optimization)
|
||||
# @example -ol high
|
||||
# @example -detail
|
||||
# @example -timing
|
||||
MAP_OPTS =
|
||||
|
||||
# Options for the PAR tool
|
||||
# @example -mt 2 (multi-threading with 2 threads)
|
||||
# @example -ol high
|
||||
PAR_OPTS =
|
||||
|
||||
# Options for the BitGen tool
|
||||
# @example -g Compress (compress bitstream)
|
||||
# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
|
||||
# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
|
||||
BITGEN_OPTS = -g StartupClk:JtagClk
|
||||
|
||||
# Options for the Trace tool
|
||||
# TRACE_OPTS =
|
||||
|
||||
# Options for the Fuse tool
|
||||
# FUSE_OPTS =
|
||||
|
||||
# Options for the ISim simulator
|
||||
# @example -gui (start the simulator in GUI mode)
|
||||
# ISIM_OPTS =
|
||||
|
||||
# Options for the ISim batch file
|
||||
# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
|
||||
# ISIM_CMD =
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
|
||||
## Programmer settings.. ##
|
||||
|
||||
# The programmer to use
|
||||
# @example impact | digilent | xc3sprog
|
||||
# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
|
||||
PROGRAMMER =
|
||||
|
||||
## Digilent JTAG cable settings
|
||||
|
||||
# @remark Use the `djtgcfg enum` command to list all available devices
|
||||
# DJTG_DEVICE = DOnbUsb
|
||||
|
||||
# The index of the JTAG device for the `prog` target
|
||||
# DJTG_INDEX = 0
|
||||
|
||||
# The index of the flash device for the `flash` target
|
||||
# DJTG_FLASH_INDEX = 1
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
Reference in New Issue
Block a user