110 lines
2.9 KiB
Plaintext
110 lines
2.9 KiB
Plaintext
## Main settings.. ##
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# Project name
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# @remark The name of the project is used as default name for the top module and the ucf file
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PROJECT =
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# Target device
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# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
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TARGET_PART =
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# Path to the Xilinx ISE installation
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XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
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# Optional the name of the top module (default is the project name)
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# TOPLEVEL =
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# Optional the path/name of the ucf file (default is the project name)
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# CONSTRAINTS =
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# Optional a target to copy the bit file to (make copy)
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# COPY_TARGET_DIR =
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## ## ## ## ## ## ## ##
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# ---------------------
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## Source files settings.. ##
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# The source files to be compiled
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# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
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# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
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## Test files settings.. ##
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# The testbench files to be compiled
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# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
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# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
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## ## ## ## ## ## ## ##
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# ---------------------
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## ISE executable settings.. ##
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# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
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# COMMON_OPTS =
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# Options for the XST synthesizer
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# @example -register_balancing (yes|no)
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# @example -opt_mode (speed|area)
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# @example -opt_level (1|2)
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XST_OPTS =
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# Options for the NGDBuild tool
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# NGDBUILD_OPTS =
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# Options for the MAP tool
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# @example -mt 2 (multi-threading with 2 threads)
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# @example -cm speed (speed optimization)
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# @example -ol high
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# @example -detail
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# @example -timing
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MAP_OPTS =
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# Options for the PAR tool
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# @example -mt 2 (multi-threading with 2 threads)
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# @example -ol high
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PAR_OPTS =
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# Options for the BitGen tool
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# @example -g Compress (compress bitstream)
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# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
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# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
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BITGEN_OPTS = -g StartupClk:JtagClk
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# Options for the Trace tool
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# TRACE_OPTS =
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# Options for the Fuse tool
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# FUSE_OPTS =
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# Options for the ISim simulator
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# @example -gui (start the simulator in GUI mode)
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# ISIM_OPTS =
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# Options for the ISim batch file
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# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
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# ISIM_CMD =
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## ## ## ## ## ## ## ##
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# ---------------------
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## Programmer settings.. ##
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# The programmer to use
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# @example impact | digilent | xc3sprog
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# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
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PROGRAMMER =
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## Digilent JTAG cable settings
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# @remark Use the `djtgcfg enum` command to list all available devices
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# DJTG_DEVICE = DOnbUsb
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# The index of the JTAG device for the `prog` target
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# DJTG_INDEX = 0
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# The index of the flash device for the `flash` target
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# DJTG_FLASH_INDEX = 1
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## ## ## ## ## ## ## ##
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# --------------------- |