MaxP
aae0a66fec
Introduces conditional logic to handle cases with zero pipeline stages, improving adaptability. Adds default values for generics and ports to enhance usability and reduce configuration errors. Cleans up formatting for better readability and maintainability. Relates to improved design modularity.
119 lines
5.7 KiB
VHDL
119 lines
5.7 KiB
VHDL
----------------------------------------------------------------------------------
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--@ - Name: **Pipeline Register**
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--@ - Version: 0.0.1
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--@ - Author: _Maximilian Passarello ([Blog](mpassarello.de))_
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--@ - License: [MIT](LICENSE)
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--@
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--@ The pipeline register provides a simple way to pipeline combinatorial logic using the **register rebalancing** of the synthesis.
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--@
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--@ ### Core functions
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--@
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--@ - **Register rebalancing**: The generic `G_RegisterBalancing` can be used
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--@ to precisely configure how register rebalancing works.
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--@ - **Number of registers**: The pipeline register instantiates a number of FFs corresponding
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--@ to the generic `G_PipelineStages`.
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--@ - **Data width**: The data width of the registers
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--@ and the input/output vectors (std_logic_vector) is configured via the generic `G_Width`.
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--@
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--@ ### Register rebalancing
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--@
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--@ The generic `G_RegisterBalancing` can be used to set the **Register Rebalancing** of the Xilinx ISE.
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--@ The possible variants are
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--@ - `no`: Deactivates the rebalancing register.
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--@ - `yes`: Activates the rebalancing register in both directions (forwards and backwards).
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--@ - `forward`: Activates the rebalancing register in the forward direction.
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--@ This causes the synthesis to shift and reduce a **multiple** of FFs at the inputs of a LUT
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--@ to a **single** FF forward at the output of a LUT.
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--@ - `backward`: Activates the rebalancing register in the backward direction.
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--@ This causes the synthesis to shift and duplicate a **single** FF at the output of a LUT
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--@ backwards to a **multiple** of FFs at the input of a LUT.
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--@
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--@ ## History
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--@ - 0.0.1 (2024-03-24) Initial version
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PipelineRegister is
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generic (
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--@ Number of pipeline stages (Correspondent to the number of registers in the pipeline)
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G_PipelineStages : integer := 3;
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--@ Data width
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G_Width : integer := 32;
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--@ Register balancing attribute<br>
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--@ - `no` : **Disable** register balancing, <br>
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--@ - `yes`: **Enable** register balancing in both directions, <br>
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--@ - `forward`: **Enable** register balancing
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--@ and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br>
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--@ - `backward`: **Enable** register balancing
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--@ and moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "yes"
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);
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port (
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--@ Clock; (**Rising edge** triggered)
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I_CLK : in std_logic := '0';
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--@ Enable input from **Pipeline Controller**
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I_Enable : in std_logic := '0';
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--@ Data input
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I_Data : in std_logic_vector(G_Width - 1 downto 0) := (others => '0');
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--@ Data output
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O_Data : out std_logic_vector(G_Width - 1 downto 0) := (others => '0')
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);
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end entity PipelineRegister;
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architecture RTL of PipelineRegister is
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attribute register_balancing : string;
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--@ Pipeline register data type; organized as an array (Stages) of std_logic_vector (Data).
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type T_Data is array(0 to G_PipelineStages - 1) of std_logic_vector(G_Width - 1 downto 0);
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--@ Pipeline register data signal; `G_PipelineStages` stages of `G_Width` bits.
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signal R_Data : T_Data := (others => (others => '0'));
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--@ Pipeline register balancing attribute from generic
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attribute register_balancing of R_Data : signal is G_RegisterBalancing;
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begin
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--@ Generate the pipeline registers if `G_PipelineStages` is greater than 0.
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GEN_PipelineRegister : if G_PipelineStages > 0 generate
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--@ Pipeline register and connection of the data from the input port to the first stage of the pipeline register. <br>
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--@ **I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1)** -> O_Data
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P_PipelineRegister : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_Enable = '1' then
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for i in 0 to G_PipelineStages - 1 loop
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if i = 0 then
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--@ Input data from the input port to the first stage of the pipeline register
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R_Data(i) <= I_Data;
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else
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--@ Data from the previous stage of the pipeline register to the current stage
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R_Data(i) <= R_Data(i - 1);
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end if;
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end loop;
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end if;
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end if;
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end process;
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end generate;
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--@ Generate the connection last register to the output port if `G_PipelineStages` is greater than 0.
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GEN_ForwardRegister : if G_PipelineStages > 0 generate
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--@ Connect (combinatoric) data from the last stage of the pipeline register to the output port. <br>
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--@ I_Data -> R_Data(0) -> R_Data(1) -> ... -> **R_Data(G_PipelineStages - 1) -> O_Data**
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P_ForwardData : process (R_Data)
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begin
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O_Data <= R_Data(G_PipelineStages - 1);
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end process;
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end generate;
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--@ Generate the connection of the input port to the output port if `G_PipelineStages` is 0.
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GEN_ForwardData : if G_PipelineStages = 0 generate
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--@ If `G_PipelineStages` is 0, the data from the input port is directly connected to the output port.
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P_ForwardData : process (I_Data)
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begin
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O_Data <= I_Data;
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end process;
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end generate;
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end architecture RTL;
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