118 lines
3.8 KiB
VHDL
118 lines
3.8 KiB
VHDL
--@ Performance Benchmarking Environment
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--@ This file is a wrapper for the module which is to be tested
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--@ and capsulates the module with flip-flops to create a synchronous
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--@ interface for the module. This is necessary to test the synthesis
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--@ results of the module.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity Pipeline_pb is
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generic (
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--@ Number of pipeline stages
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G_PipelineStages : integer := 3;
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--@ Data width
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G_Width : integer := 32;
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--@ Register balancing attribute<br>
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--@ - "no" : No register balancing <br>
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--@ - "yes": Register balancing in both directions <br>
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--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
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--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "yes"
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);
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port (
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I_CLK : in std_logic;
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I_RST : in std_logic;
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I_CE : in std_logic;
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I_Data : in std_logic_vector(G_Width - 1 downto 0);
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I_Valid : in std_logic;
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O_Ready : out std_logic;
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O_Data : out std_logic_vector(G_Width - 1 downto 0);
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O_Valid : out std_logic;
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I_Ready : in std_logic
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);
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end entity Pipeline_pb;
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architecture RTL of Pipeline_pb is
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-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
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attribute keep : string;
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-- IOB attribute: Attaches the FF to the IOB if is "true".
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attribute IOB : string;
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-- General Interace
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signal R_RST : std_logic;
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signal R_CE : std_logic;
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-- Attribute
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attribute keep of R_RST, R_CE : signal is "true";
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attribute IOB of R_RST, R_CE : signal is "false";
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-- Input Interface
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signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
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signal R_ValidIn : std_logic;
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signal R_ReadyOut : std_logic;
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-- Attribute
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attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
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attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
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-- Output Interface
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signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
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signal R_ValidOut : std_logic;
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signal R_ReadyIn : std_logic;
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-- Attribute
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attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
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attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
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signal C_PipelineEnable : std_logic;
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begin
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BenchmarkEnvironmentFFs : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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-- General Interace
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R_RST <= I_RST;
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R_CE <= I_CE;
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-- Input Interface
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R_DataIn <= I_Data;
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R_ValidIn <= I_Valid;
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O_Ready <= R_ReadyOut;
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-- Output Interface
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O_Data <= R_DataOut;
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O_Valid <= R_ValidOut;
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R_ReadyIn <= I_Ready;
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end if;
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end process;
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PipelineController : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => R_RST,
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I_CE => R_CE,
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O_Enable => C_PipelineEnable,
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I_Valid => R_ValidIn,
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O_Ready => R_ReadyOut,
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O_Valid => R_ValidOut,
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I_Ready => R_ReadyIn
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);
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PipelineRegister : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_PipelineEnable,
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I_Data => R_DataIn,
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O_Data => R_DataOut
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);
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end architecture RTL; |