HDL/Pipeline-AXI-Handshake
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base: HDL:c51815cb51215706a2ee617c1f637021ecd90799
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HDL:main
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compare: HDL:506f2edabbda0b9df75c0208a54ac974d35c80fd
Branches Tags
HDL:main

5 Commits
c51815cb51 ... 506f2edabb

Author SHA1 Message Date
Max P
506f2edabb fix: Corrects ready signal and data buffering logic 
- Corrects the ready signal to properly reflect buffer status.
- Modifies data buffering logic to ensure proper data handling.
- Updates the ready signal to high when buffer is not full.
 2025-07-11 10:17:37 +00:00
Max P
5e1a3c2161 refactor: adjusts pipeline parameters for performance 
- Changes clock frequency to 280 MHz.
- Reduces pipeline module count to improve performance.
 2025-07-11 10:15:49 +00:00
Max P
88753b62f4 feat: implements pipelined module chaining for performance 
- Introduces a pipelined module and top-level wrapper for
  performance benchmarking.
- Chains multiple pipeline modules in series to increase throughput.
- Adds generics to control pipeline depth, data width, and
  register balancing.
- Includes optional CE/RST enables and pipeline buffer.
 2025-07-11 10:05:02 +00:00
Max P
96833c0f77 test: Updates waveform configuration for testbench 
- Corrects signal names in the waveform configuration file.
- Adds individual bit signals for output data.
 2025-07-11 10:03:32 +00:00
Max P
caff24255d Refactor: Reduces maximum fanout for nets 
- Reduces the maximum allowed fanout value to improve timing
  closure.
- This change aims to optimize resource utilization.
 2025-07-11 10:03:18 +00:00
6 changed files with 380 additions and 116 deletions
Expand all files Collapse all files

2
project.yml
View File

@@ -249,7 +249,7 @@ tool_options:
# Maximum allowed fanout for a net. # Maximum allowed fanout for a net.
# Values: integer (e.g., 500) # Values: integer (e.g., 500)
- "-max_fanout 500" - "-max_fanout 50"
# Maximum number of BUFGs (global buffers) to use. # Maximum number of BUFGs (global buffers) to use.
# Values: 0–32 (device-dependent) # Values: 0–32 (device-dependent)

8
src/PipelineBufferController.vhd
View File

@@ -41,27 +41,31 @@ architecture RTL of PipelineBufferController is
signal C_Enable : std_logic := '0'; signal C_Enable : std_logic := '0';
signal R_IsBuffered : std_logic := '0'; signal R_IsBuffered : std_logic := '0';
signal R_Ready : std_logic := '1';
begin begin
--@ Set mux to buffered mode if data is available in the buffer. --@ Set mux to buffered mode if data is available in the buffer.
C_MUX <= R_IsBuffered; C_MUX <= R_IsBuffered;
--@ Enable the buffer register if not buffered and chip enable is high. --@ Enable the buffer register if not buffered and chip enable is high.
C_Enable <= I_CE and not R_IsBuffered; C_Enable <= I_CE and not R_IsBuffered;
--@ Set the ready signal to high if not buffered.
O_Ready <= not R_IsBuffered;
--@ Set the valid signal to high if data is available in the buffer or if data is valid. --@ Set the valid signal to high if data is available in the buffer or if data is valid.
O_Valid <= R_IsBuffered or I_Valid; O_Valid <= R_IsBuffered or I_Valid;
O_Ready <= R_Ready;
process (I_CLK) process (I_CLK)
begin begin
if rising_edge(I_CLK) then if rising_edge(I_CLK) then
if I_RST = G_ResetActiveAt then if I_RST = G_ResetActiveAt then
R_IsBuffered <= '0'; R_IsBuffered <= '0';
R_Ready <= '1';
elsif I_CE = '1' then elsif I_CE = '1' then
if R_IsBuffered = '0' and I_Valid = '1' then if R_IsBuffered = '0' and I_Valid = '1' then
R_IsBuffered <= '1'; R_IsBuffered <= '1';
R_Ready <= '0';
elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
R_IsBuffered <= '0'; R_IsBuffered <= '0';
R_Ready <= '1';
end if; end if;
end if; end if;
end if; end if;

2
src/Pipeline_pb.ucf
View File

@@ -1,4 +1,4 @@
#NET I_CLK LOC = AG18; #NET I_CLK LOC = AG18;
NET I_CLK LOC = B8; NET I_CLK LOC = B8;
NET I_CLK TNM_NET = CLOCK; NET I_CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %; TIMESPEC TS_CLOCK = PERIOD CLOCK 280 MHz HIGH 50 %;

177
src/Pipeline_pb.vhd
View File

@@ -11,24 +11,36 @@ use ieee.math_real.all;
entity Pipeline_pb is entity Pipeline_pb is
generic ( generic (
--@ Number of pipeline stages --@ Number of pipeline stages inside each module
G_PipelineStages : integer := 10; G_PipelineStages : integer := 2;
--@ Data width --@ Data width
G_Width : integer := 32; G_Width : integer := 8;
--@ Register balancing attribute<br> --@ Register balancing attribute<br>
--@ - "no" : No register balancing <br> --@ - "no" : No register balancing <br>
--@ - "yes": Register balancing in both directions <br> --@ - "yes": Register balancing in both directions <br>
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br> --@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs. --@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "yes" G_RegisterBalancing : string := "yes";
--@ Enable pipeline buffer
--@ - true : Use pipeline buffer
--@ - false : Direct connection (bypass)
G_EnablePipelineBuffer : boolean := true;
--@ How many Pipeline modules shall be chained?
G_PipelineModules : integer := 20;
--@ Enable chip enable signal
G_Enable_CE : boolean := false;
--@ Enable reset signal
G_Enable_RST : boolean := false
); );
port ( port (
I_CLK : in std_logic; I_CLK : in std_logic;
I_RST : in std_logic; I_RST : in std_logic;
I_CE : in std_logic; I_CE : in std_logic;
---
I_Data : in std_logic_vector(G_Width - 1 downto 0); I_Data : in std_logic_vector(G_Width - 1 downto 0);
I_Valid : in std_logic; I_Valid : in std_logic;
O_Ready : out std_logic; O_Ready : out std_logic;
---
O_Data : out std_logic_vector(G_Width - 1 downto 0); O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic; O_Valid : out std_logic;
I_Ready : in std_logic I_Ready : in std_logic
@@ -36,119 +48,116 @@ entity Pipeline_pb is
end entity Pipeline_pb; end entity Pipeline_pb;
architecture RTL of Pipeline_pb is architecture RTL of Pipeline_pb is
-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true". ---------------------------------------------------------------------------
-- Attribute helpers
---------------------------------------------------------------------------
attribute keep : string; attribute keep : string;
-- IOB attribute: Attaches the FF to the IOB if is "true".
attribute IOB : string; attribute IOB : string;
-- General Interace ---------------------------------------------------------------------------
signal R_RST : std_logic; -- Bench‐wrapper FFs (synchronous IO)
signal R_CE : std_logic; ---------------------------------------------------------------------------
-- Attribute signal R_RST : std_logic := '0';
signal R_CE : std_logic := '1';
attribute keep of R_RST, R_CE : signal is "true"; attribute keep of R_RST, R_CE : signal is "true";
attribute IOB of R_RST, R_CE : signal is "false"; attribute IOB of R_RST, R_CE : signal is "false";
-- Input Interface signal R_DataIn : std_logic_vector(G_Width-1 downto 0);
signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
signal R_ValidIn : std_logic; signal R_ValidIn : std_logic;
signal R_ReadyOut : std_logic; attribute keep of R_DataIn, R_ValidIn : signal is "true";
-- Attribute attribute IOB of R_DataIn, R_ValidIn : signal is "false";
attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
-- Output Interface signal R_DataOut : std_logic_vector(G_Width-1 downto 0);
signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
signal R_ValidOut : std_logic; signal R_ValidOut : std_logic;
signal R_ReadyIn : std_logic; signal R_ReadyIn : std_logic;
-- Attribute
attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true"; attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false"; attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
signal C_Pipeline0Enable : std_logic; ---------------------------------------------------------------------------
signal C_Pipeline1Enable : std_logic; -- Chaining arrays (sentinel element @0 and @G_PipelineModules)
---------------------------------------------------------------------------
type T_DataArray is array(0 to G_PipelineModules) of std_logic_vector(G_Width-1 downto 0);
signal S_Data : T_DataArray;
signal S_Valid : std_logic_vector(0 to G_PipelineModules);
signal S_Ready : std_logic_vector(0 to G_PipelineModules);
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
begin begin
GEN_Enable_CE : if G_Enable_CE = true generate
BenchmarkEnvironmentFFs : process (I_CLK) process(I_CLK)
begin begin
if rising_edge(I_CLK) then if rising_edge(I_CLK) then
-- General Interace
R_RST <= I_RST;
R_CE <= I_CE; R_CE <= I_CE;
end if;
end process;
end generate GEN_Enable_CE;
-- Input Interface GEN_Enable_RST : if G_Enable_RST = true generate
process(I_CLK)
begin
if rising_edge(I_CLK) then
R_RST <= I_RST;
end if;
end process;
end generate GEN_Enable_RST;
-----------------------------------------------------------------------
-- Wrapper FFs: register all top‑level ports once for fair timing
-----------------------------------------------------------------------
BenchFF : process(I_CLK)
begin
if rising_edge(I_CLK) then
--- Register inputs
R_DataIn <= I_Data; R_DataIn <= I_Data;
R_ValidIn <= I_Valid; R_ValidIn <= I_Valid;
O_Ready <= R_ReadyOut; O_Ready <= S_Ready(0);
--- Register outputs
-- Output Interface R_DataOut <= S_Data (G_PipelineModules);
O_Data <= R_DataOut; R_ValidOut <= S_Valid(G_PipelineModules);
O_Valid <= R_ValidOut;
R_ReadyIn <= I_Ready; R_ReadyIn <= I_Ready;
end if; end if;
end process; end process;
PipelineControllerIn : entity work.PipelineController O_Data <= R_DataOut;
O_Valid <= R_ValidOut;
-----------------------------------------------------------------------
-- Bind sentinel 0 with registered inputs
-----------------------------------------------------------------------
S_Data (0) <= R_DataIn;
S_Valid(0) <= R_ValidIn;
-----------------------------------------------------------------------
-- Bind last sentinel with registered outputs
-----------------------------------------------------------------------
S_Ready(G_PipelineModules) <= R_ReadyIn;
-----------------------------------------------------------------------
-- Generate N pipeline modules in series
-----------------------------------------------------------------------
gen_modules : for i in 0 to G_PipelineModules-1 generate
P_MOD : entity work.Pipeline_pb_Module
generic map( generic map(
G_PipelineStages => G_PipelineStages, G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1' G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing,
G_EnablePipelineBuffer => G_EnablePipelineBuffer
) )
port map( port map(
I_CLK => I_CLK, I_CLK => I_CLK,
I_RST => R_RST, I_RST => R_RST,
I_CE => R_CE, I_CE => R_CE,
O_Enable => C_Pipeline0Enable, -- Up‑stream side
I_Valid => R_ValidIn, I_Data => S_Data (i),
O_Ready => R_ReadyOut, I_Valid => S_Valid(i),
O_Valid => R_Valid, O_Ready => S_Ready(i),
I_Ready => R_Ready -- Down‑stream side
O_Data => S_Data (i+1),
O_Valid => S_Valid(i+1),
I_Ready => S_Ready(i+1)
); );
PipelineRegisterIn : entity work.PipelineRegister end generate gen_modules;
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline0Enable,
I_Data => R_DataIn,
O_Data => R_Data
);
---------
PipelineControllerOut : entity work.PipelineController
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
I_CE => R_CE,
O_Enable => C_Pipeline1Enable,
I_Valid => R_Valid,
O_Ready => R_Ready,
O_Valid => R_ValidOut,
I_Ready => R_ReadyIn
);
PipelineRegisterOut : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline1Enable,
I_Data => R_Data,
O_Data => R_DataOut
);
end architecture RTL; end architecture RTL;

123
src/Pipeline_pb_Module.vhd Normal file
View File

@@ -0,0 +1,123 @@
--@ Performance Benchmarking Environment
--@ This file is a wrapper for the module which is to be tested
--@ and capsulates the module with flip-flops to create a synchronous
--@ interface for the module. This is necessary to test the synthesis
--@ results of the module.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Pipeline_pb_Module is
generic (
--@ Number of pipeline stages
G_PipelineStages : integer := 10;
--@ Data width
G_Width : integer := 32;
--@ Register balancing attribute<br>
--@ - "no" : No register balancing <br>
--@ - "yes": Register balancing in both directions <br>
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "no";
--@ Enable pipeline buffer
--@ - true : Use pipeline buffer
--@ - false : Direct connection (bypass)
G_EnablePipelineBuffer : boolean := false
);
port (
I_CLK : in std_logic;
I_RST : in std_logic;
I_CE : in std_logic;
I_Data : in std_logic_vector(G_Width - 1 downto 0);
I_Valid : in std_logic;
O_Ready : out std_logic;
O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic;
I_Ready : in std_logic
);
end entity Pipeline_pb_Module;
architecture RTL of Pipeline_pb_Module is
signal C_Pipeline0Enable : std_logic;
signal C_PipelineBufferEnable : std_logic_vector(1 downto 0) := (others => '0');
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
signal C_Data : std_logic_vector(G_Width - 1 downto 0);
begin
PipelineControllerIn : entity work.PipelineController
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => I_RST,
I_CE => I_CE,
O_Enable => C_Pipeline0Enable,
I_Valid => I_Valid,
O_Ready => O_Ready,
O_Valid => R_Valid,
I_Ready => R_Ready
);
PipelineRegisterIn : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline0Enable,
I_Data => I_Data,
O_Data => R_Data
);
---------
C_Data <= std_logic_vector(unsigned(R_Data) + 3); -- Example operation, can be replaced with actual logic
---------
-- Pipeline Buffer Generation based on G_EnablePipelineBuffer
gen_pipeline_buffer : if G_EnablePipelineBuffer generate
PipelineBufferController : entity work.PipelineBufferController
generic map(
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => I_RST,
I_CE => I_CE,
O_Enable => C_PipelineBufferEnable,
I_Valid => R_Valid,
O_Ready => R_Ready,
O_Valid => O_Valid,
I_Ready => I_Ready
);
PipelineBuffer : entity work.PipelineBuffer
generic map(
G_Width => G_Width
)
port map(
I_CLK => I_CLK,
I_Enable => C_PipelineBufferEnable,
I_Data => C_Data,
O_Data => O_Data
);
end generate gen_pipeline_buffer;
-- Direct connection when pipeline buffer is disabled
gen_direct_connection : if not G_EnablePipelineBuffer generate
-- Direct signal connections (bypass pipeline buffer)
O_Valid <= R_Valid;
O_Data <= R_Data;
R_Ready <= I_Ready;
end generate gen_direct_connection;
end architecture RTL;

140
tests/PipelineBuffer_tb.wcfg
View File

@@ -51,9 +51,9 @@
<obj_property name="ElementShortName">o_ready</obj_property> <obj_property name="ElementShortName">o_ready</obj_property>
<obj_property name="ObjectShortName">o_ready</obj_property> <obj_property name="ObjectShortName">o_ready</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data" type="array" db_ref_id="1"> <wvobject fp_name="/pipelinebuffer_tb/i_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_data[31:0]</obj_property> <obj_property name="ElementShortName">i_data[31:0]</obj_property>
<obj_property name="ObjectShortName">o_data[31:0]</obj_property> <obj_property name="ObjectShortName">i_data[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="divider12" type="divider"> <wvobject fp_name="divider12" type="divider">
@@ -70,10 +70,138 @@
<obj_property name="ElementShortName">i_ready</obj_property> <obj_property name="ElementShortName">i_ready</obj_property>
<obj_property name="ObjectShortName">i_ready</obj_property> <obj_property name="ObjectShortName">i_ready</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/pipelinebuffer_tb/i_data" type="array" db_ref_id="1"> <wvobject fp_name="/pipelinebuffer_tb/o_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_data[31:0]</obj_property> <obj_property name="ElementShortName">o_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_data[31:0]</obj_property> <obj_property name="ObjectShortName">o_data[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<wvobject fp_name="/pipelinebuffer_tb/o_data[31]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[31]</obj_property>
<obj_property name="ObjectShortName">o_data[31]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[30]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[30]</obj_property>
<obj_property name="ObjectShortName">o_data[30]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[29]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[29]</obj_property>
<obj_property name="ObjectShortName">o_data[29]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[28]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[28]</obj_property>
<obj_property name="ObjectShortName">o_data[28]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[27]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[27]</obj_property>
<obj_property name="ObjectShortName">o_data[27]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[26]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[26]</obj_property>
<obj_property name="ObjectShortName">o_data[26]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[25]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[25]</obj_property>
<obj_property name="ObjectShortName">o_data[25]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[24]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[24]</obj_property>
<obj_property name="ObjectShortName">o_data[24]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[23]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[23]</obj_property>
<obj_property name="ObjectShortName">o_data[23]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[22]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[22]</obj_property>
<obj_property name="ObjectShortName">o_data[22]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[21]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[21]</obj_property>
<obj_property name="ObjectShortName">o_data[21]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[20]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[20]</obj_property>
<obj_property name="ObjectShortName">o_data[20]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[19]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[19]</obj_property>
<obj_property name="ObjectShortName">o_data[19]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[18]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[18]</obj_property>
<obj_property name="ObjectShortName">o_data[18]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[17]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[17]</obj_property>
<obj_property name="ObjectShortName">o_data[17]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[16]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[16]</obj_property>
<obj_property name="ObjectShortName">o_data[16]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[15]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">o_data[15]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[14]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">o_data[14]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[13]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">o_data[13]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[12]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">o_data[12]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[11]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">o_data[11]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[10]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">o_data[10]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[9]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">o_data[9]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[8]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">o_data[8]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[7]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">o_data[7]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[6]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">o_data[6]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[5]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">o_data[5]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[4]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">o_data[4]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[3]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">o_data[3]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[2]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">o_data[2]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[1]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">o_data[1]</obj_property>
</wvobject>
<wvobject fp_name="/pipelinebuffer_tb/o_data[0]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">o_data[0]</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="group15" type="group"> <wvobject fp_name="group15" type="group">
<obj_property name="label">Buffer</obj_property> <obj_property name="label">Buffer</obj_property>