HDL/Pipeline-AXI-Handshake
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# Entity: PipelineController
- **File**: PipelineController.vhd
## Diagram
![Diagram](PipelineController.svg "Diagram")
## Generics
| Generic name | Type | Value | Description |
| ---------------- | --------- | ----- | ------------------------- |
| G_PipelineStages | integer | 3 | Number of pipeline stages |
| G_ResetActiveAt | std_logic | '1' | Reset active at: |
## Ports
| Port name | Direction | Type | Description |
| -------------------- | --------- | ----------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
| I_RST | in | std_logic | Reset signal; Active at `G_ResetActiveAt` |
| I_CE | in | std_logic | Chip enable; Active high |
| O_Enable | out | std_logic | Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br> **Note:** Connect to `I_Enable` of the registers to be controlled by this controller. |
| Input-AXI-Handshake | in | Virtual bus | Input AXI like Handshake |
| Output-AXI-Handshake | out | Virtual bus | Output AXI like Handshake |
### Virtual Buses
#### Input-AXI-Handshake
| Port name | Direction | Type | Description |
| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
| I_Valid | in | std_logic | Valid data flag; indicates that the data on `I_Data` of the connected registers is valid. |
| O_Ready | out | std_logic | Ready flag; indicates that the connected registers is ready to accept data. |
#### Output-AXI-Handshake
| Port name | Direction | Type | Description |
| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
| O_Valid | out | std_logic | Valid data flag; indicates that the data on `O_Data` of the connected registers is valid. |
| I_Ready | in | std_logic | Ready flag; indicates that the external component is ready to accept data. |
## Signals
| Name | Type | Description |
| ------- | ----------------------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------- |
| R_Valid | std_logic_vector(G_PipelineStages - 1 downto 0) | Pipeline ready signal for each stage of the pipeline to indicate that the data in pipeline is valid |
| C_Ready | std_logic | Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br> mapped to `O_Enable` and `O_Ready` ports. |
## Processes
- P_Flags: ( R_Valid, I_Ready )
- **Description**
Produce the `C_Ready` signal for the pipeline controller, controlling the data flow in the pipeline.
- P_ValidPipeline: ( I_CLK )
- **Description**
Shift the pipeline stages with `R_Valid` signal as placeholder to control the pipeline stages.

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# Entity: PipelineRegister
- **File**: PipelineRegister.vhd
## Diagram
![Diagram](PipelineRegister.svg "Diagram")
## Generics
| Generic name | Type | Value | Description |
| ------------------- | ------- | ----- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| G_PipelineStages | integer | 3 | Number of pipeline stages |
| G_Width | integer | 32 | Data width |
| G_RegisterBalancing | string | "yes" | Register balancing attribute<br> - "no" : **Disable** register balancing, <br> - "yes": **Enable** register balancing in both directions, <br> - "forward": **Enable** and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br> - "backward": **Enable** and moves a single FF at the output of a LUT to a set of FFs at its inputs. |
## Ports
| Port name | Direction | Type | Description |
| --------- | --------- | -------------------------------------- | ----------------------------------------- |
| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
| I_Enable | in | std_logic | Enable input from **Pipeline Controller** |
| I_Data | in | std_logic_vector(G_Width - 1 downto 0) | Data input |
| O_Data | out | std_logic_vector(G_Width - 1 downto 0) | Data output |
## Signals
| Name | Type | Description |
| ------ | ------ | --------------------------------------------------------------------------- |
| R_Data | T_Data | Pipeline register data signal; `G_PipelineStages` stages of `G_Width` bits. |
## Types
| Name | Type | Description |
| ------ | ---- | --------------------------------------------------------------------------------------- |
| T_Data | | Pipeline register data type; organized as an array (Stages) of std_logic_vector (Data). |
## Processes
- P_PipelineRegister: ( I_CLK )
- **Description**
Pipeline register I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1) -> O_Data

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