HDL/Pipeline-AXI-Handshake
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Enhance Pipeline Controller and Register with AXI-Like Handshaking and Register Rebalancing

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- Introduce comprehensive documentation for Pipeline Controller and Register, detailing core functions, generics, ports, and processes. Focus on data flow control, validity control, adjustability, and register rebalancing mechanisms.
- Implement AXI-Like handshaking in Pipeline Controller for improved input and output data handling, supporting active-high ready and valid signals for efficient data transfer.
- Refine Pipeline Register with register rebalancing options (no, yes, forward, backward) to optimize combinatorial logic pipelining in synthesis, configurable via `G_RegisterBalancing` generic.
- Update generics and ports descriptions to reflect the inclusion of I/O FFs in pipeline depth calculation and clarify the reset active level and handshaking protocol.
- Extend VHDL source for both modules to embody described functionalities and adjustments, ensuring alignment with documentation enhancements.
- Augment testbench `Pipeline_tb.vhd` with random intervals for write and read operations, emphasizing dynamic testing scenarios.
This commit is contained in:
0xMax42
2024-03-24 19:47:01 +01:00
parent e03dc4e0c8
commit abb4a9f10a
6 changed files with 350 additions and 101 deletions
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57
src/PipelineRegister.vhd
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@@ -1,3 +1,36 @@
----------------------------------------------------------------------------------
--@ - Name: **Pipeline Register**
--@ - Version: 0.0.1
--@ - Author: _Maximilian Passarello ([Blog](mpassarello.de))_
--@ - License: [MIT](LICENSE)
--@
--@ The pipeline register provides a simple way to pipeline combinatorial logic using the **register rebalancing** of the synthesis.
--@
--@ ### Core functions
--@
--@ - **Register rebalancing**: The generic `G_RegisterBalancing` can be used
--@ to precisely configure how register rebalancing works.
--@ - **Number of registers**: The pipeline register instantiates a number of FFs corresponding
--@ to the generic `G_PipelineStages`.
--@ - **Data width**: The data width of the registers
--@ and the input/output vectors (std_logic_vector) is configured via the generic `G_Width`.
--@
--@ ### Register rebalancing
--@
--@ The generic `G_RegisterBalancing` can be used to set the **Register Rebalancing** of the Xilinx ISE.
--@ The possible variants are
--@ - `no`: Deactivates the rebalancing register.
--@ - `yes`: Activates the rebalancing register in both directions (forwards and backwards).
--@ - `forward`: Activates the rebalancing register in the forward direction.
--@ This causes the synthesis to shift and reduce a **multiple** of FFs at the inputs of a LUT
--@ to a **single** FF forward at the output of a LUT.
--@ - `backward`: Activates the rebalancing register in the backward direction.
--@ This causes the synthesis to shift and duplicate a **single** FF at the output of a LUT
--@ backwards to a **multiple** of FFs at the input of a LUT.
--@
--@ ## History
--@ - 0.0.1 (2024-03-24) Initial version
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -5,15 +38,17 @@ use ieee.math_real.all;
entity PipelineRegister is
generic (
--@ Number of pipeline stages
--@ Number of pipeline stages (Correspondent to the number of registers in the pipeline)
G_PipelineStages : integer := 3;
--@ Data width
G_Width : integer := 32;
--@ Register balancing attribute<br>
--@ - "no" : **Disable** register balancing, <br>
--@ - "yes": **Enable** register balancing in both directions, <br>
--@ - "forward": **Enable** and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br>
--@ - "backward": **Enable** and moves a single FF at the output of a LUT to a set of FFs at its inputs.
--@ - `no` : **Disable** register balancing, <br>
--@ - `yes`: **Enable** register balancing in both directions, <br>
--@ - `forward`: **Enable** register balancing
--@ and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br>
--@ - `backward`: **Enable** register balancing
--@ and moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "yes"
);
port (
@@ -39,15 +74,18 @@ architecture RTL of PipelineRegister is
attribute register_balancing of R_Data : signal is G_RegisterBalancing;
begin
--@ Pipeline register I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1) -> O_Data
--@ Pipeline register and connection of the data from the input port to the first stage of the pipeline register. <br>
--@ **I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1)** -> O_Data
P_PipelineRegister : process (I_CLK)
begin
if rising_edge(I_CLK) then
if I_Enable = '1' then
for i in 0 to G_PipelineStages - 1 loop
if i = 0 then
--@ Input data from the input port to the first stage of the pipeline register
R_Data(i) <= I_Data;
else
--@ Data from the previous stage of the pipeline register to the current stage
R_Data(i) <= R_Data(i - 1);
end if;
end loop;
@@ -55,6 +93,11 @@ begin
end if;
end process;
O_Data <= R_Data(G_PipelineStages - 1);
--@ Connect (combinatoric) data from the last stage of the pipeline register to the output port. <br>
--@ I_Data -> R_Data(0) -> R_Data(1) -> ... -> **R_Data(G_PipelineStages - 1) -> O_Data**
P_ForwardData : process (R_Data)
begin
O_Data <= R_Data(G_PipelineStages - 1);
end process;
end architecture RTL;